HSP50214BVI Intersil, HSP50214BVI Datasheet - Page 10

• Manufacturer Part Number: HSP50214BVI
• Manufacturer: Intersil

Specifications of HSP50214BVI

• Lead Free Status / RoHS Status: Not Compliant

See Figures 4 to 7 for an interpolated input example,
detailing the associated spectral results.
Interpolation Example:
The specifications for the interpolated input example are:
CLKIN = 40MHz
Input Sample Rate = 5MSPS
PROCCLK = 28MHz
Interpolate by 8, Decimate by 10
Desired 85dB dynamic range output bandwidth = 500kHz
Input Level Detector
The Input Level Detector Section measures the average
magnitude error at the PDC input for the microprocessor by
comparing the input level against a programmable
threshold and then integrating the result. It is intended to
provide a gain error for use in an AGC loop with either the
RF/IF or A/D converter stages (see Figure 8). The AGC
loop includes Input Level Detector, the microprocessor and
an external gain control amplifier (or attenuator). The input
samples are rectified and added to a threshold
Without Interpolation, the CIC bypass path exceeds the HB/FIR filter
input sample rate and the CIC filter path will not yield the desired
85dB dynamic range band width of 500kHz.
CLKIN = 5MHz
5MHz
FIGURE 4. STATEMENT OF THE PROBLEM
IN(13:0)
MIN. R = 4
CONTROL WORD 0
CONTROL WORD 1
FILTER
BYPASS
FORMAT
CIC
INPUT
GAINADJ(2:0)
†
CLKIN
ENI
PROCCLK = 28MHz
10
MAX. f
BYPASS PATH)
HB/FIR FILTER
(EXCEEDED IN
INTERP
S
= 4MHz
FIGURE 3. BLOCK DIAGRAM OF THE INPUT SECTION
†
CONTROL
LOGIC
(NOT ACHIEVED
WITH CIC FILTER
PATH)
500kHz = 85dB
BANDWIDTH
DETECT
LEVEL
14
14
INPUT LEVEL DETECTOR
STATUS (0)
NCO
HSP50214B
EN
INPUT_MODE
INPUT_FMT
INPUT_THRESH
INTG_MODE
INTG_INTEVAL
18
DELAY 3
DELAY 3
††
INPUT_THRESH
INTG_MODE
INTG_INTEVAL
15
15
18
†
†
†
3
programmed via the microprocessor interface, as shown in
Figure 9. The bit weighting of the data path through the
input threshold detector is shown in Figure 10. The
threshold is a signed number, so it should be set to the
inverse of the desired input level. The threshold can be set
to zero if the average input level is desired instead of the
error. The sum of the threshold and the absolute value of
the input is accumulated in a 32-bit accumulator. The
accumulator can handle up to 2
overflow. The integration time is controlled by an 18-bit
counter. The integration counter preload (ICPrel) is
programmed via the microprocessor interface through
Control Word 1. Only the upper 16-bits are programmable.
The 2 LSBs are always zero. Control Word 1, Bits 29-14
are programmed to:
where N is the desired integration period, defined as the
number of input samples to be integrated. N must be a
multiple of 4: [0, 4, 8, 12, 16 .... , 2
ICPrel
†
†
†
LIMIT
↑8 (0 STUFF) = 40MHz
†
5MHz
CLKIN = 40MHz
FIGURE 5. BLOCK DIAGRAM OF THE INTERPOLATION
∑
†
†
4
4
†
=
( ) 4
N
††
CIC FILTER
⁄
†
APPROACH
See NCO Section for more details.
R = ↓10
Controlled via microprocessor interface.
+
1
BYPASS
4MHz
†
HB/FIR FILTER
18
18
samples without
].
500kHz = 85dB
BANDWIDTH
May 1, 2007
FN4450.4
(EQ. 1)