HSP50214BVI Intersil, HSP50214BVI Datasheet - Page 13

• Manufacturer Part Number: HSP50214BVI
• Manufacturer: Intersil

Specifications of HSP50214BVI

• Lead Free Status / RoHS Status: Not Compliant

Typically, the average input error is read from the Input Level
Detector port for use in AGC Applications. By setting the
threshold to 0, however, the average value of the input signal
can be read directly. The calculation is:
where “level” is the 24-bit value read from the 3 level
Detector Registers and “N” is the number of samples to be
integrated. Note that to get the RMS value of a sinusoid,
multiply the average value of the rectified sinusoid by 1.111.
For a full scale input sinusoid, this yields an RMS value of
approximately 3dBf
NOTE: 1.111 scales the rectified sinusoid average (2/π) to 1/ √2
.
In the HSP50214B, the polarity of the LSB’s of the
integration period pre-load is selectable. If Control Word 27,
Bit 23 is set to a logic one, the two LSB’s of the integration
period preload are set to logic ones. This allows a power of
two to be set for the integration period, for easy
normalization in the processor. If Control Word 27, Bit 23 is
set to a logic zero, then the two LSB’s of the integration
period preload are set to zeros as in the HSP50214.
Carrier Synthesizer/Mixer
The Carrier Synthesizer/Mixer Section of the HSP50214B is
shown in Figure 12. The NCO has a 32-bit phase
accumulator, a 10-bit phase offset adder, and a sine/cosine
ROM. The frequency of the NCO is the sum of a center
frequency Control Word, loaded via the microprocessor
interface (Control Word 3, Bits 0 to 31), and an offset
frequency, loaded serially via the COF and COFSYNC pins.
The offset frequency can be zeroed in Control Word 0, Bit 1.
Both frequency control terms are 32-bits and the addition is
A) INPUT SIGNAL
C) THRESHOLD
E) DETECTOR OUTPUT
dBFS
FIGURE 11. SIGNAL PROCESSING WITHIN LEVEL DETECTOR
RMS
=
(
20
)
log
S
[
.
(
1.111
) level
(
13
B) RECTIFIED SIGNAL
D) ACCUMULATOR INPUTS
F) CLOSED LOOP STEADY STATE
(CONSTANT INPUT)
)
⁄
(
( ) 16
N
(
)
)
]
(EQ. 2)
HSP50214B
modulo 2
as:
or in terms of the programmed value:
where N is the 32-bit sum of the center and offset frequency
terms, f
the input sampling frequency, and INT is the integer of the
computation. See the Microprocessor Write Section on
instructions for writing Control Word
†
For example, if N is 3267 (decimal), and f
is 49.44Hz. If received data is modulated at a carrier
frequency of 10MHz, then the synthesizer/mixer should be
programmed for N = 27627627 (hex) or D89D89D8 (hex).
Because the input enable, ENI, controls the operation of the
phase accumulator, the NCO output frequency is computed
relative to the input sample rate, f
frequency control, N, is interpreted as two’s complement
because the output of the NCO is quadrature. Negative
frequency L.O.s select the upper sideband; positive frequency
L.O.s select the lower sideband. The range of the NCO is
-f
or approximately 0.015Hz when CLKIN is 65MSPS and ENI is
tied low.
ENABLE
COFSYNC
f
N
SYNCIN1
C
S
Controlled via microprocessor interface.
/2 to +f
=
=
INT f
COF
COF
f
ENI
S
FIGURE 12. BLOCK DIAGRAM OF NCO SECTION
* N
C
†
[
32
S
is the frequency of the carrier NCO sinusoids, f
C
⁄
/2. The frequency resolution of the NCO is f
COF
. The output frequency of the NCO is computed
(
ACCUMULATOR
×
CIRCUITRY
SYNC
SHIFT REG
2
32
2
32
SYNC
32
PHASE
)
MUX
REG
,
⁄
f
S
0
]
HEX
COS
TO MIXERS
18
SIN/COS
18
,
32
ROM
REG
REG
REG
REG
REG
+
+
18
CF
SIN
10
CARRIER
FREQUENCY
(f
C
S
)
, not to f
G
R
E
MUX
FREQUENCY
3.
STROBE
CARRIER
STROBE
CARRIER
R
E
G
PHASE
0
S
CLKIN
†
is 65MHz, then f
G
R
E
†
†
CARRIER
PHASE
OFFSET
. The
ACCUM
May 1, 2007
CLEAR
PHASE
UPDATE
†
CARRIER
LOAD ON
(EQ. 3A)
S
FN4450.4
(EQ. 3)
/(2
S
32
†
is
C
†
)