HSP50214BVI Intersil, HSP50214BVI Datasheet - Page 39

• Manufacturer Part Number: HSP50214BVI
• Manufacturer: Intersil

Specifications of HSP50214BVI

• Lead Free Status / RoHS Status: Not Compliant

Figure 37 shows the interface between a 16-bit
microprocessor (or other baseband processing engine) and
the Buffer RAM Output Section of the Programmable Down
Converter, configured for data output via the parallel outputs
AOUT and BOUT. In the 16-bit microprocessor interface
configuration, the Buffer RAM pointer is incremented when
the μProcessor reads address SEL(2:0) = 7 and OEBL = 0.
After reset, the FIFO must be incremented to read the first
sample set. This is because the RAM read and write pointers
cannot point to the same address. Thus, the FIFO pointer
must move to the next address before reading the next set of
data (I, Q, |r|, φ, and f) samples. 4 PROCCLK cycles are
required after an increment before reading can resume. The
FIFO write pointer is reset to zero (the first data sample) when
Control Word 22 is written to via the 8-bit microprocessor
interface. See the Microprocessor Read Section for more
detail on how to obtain the Buffer RAM output with this
technique. Figure 39 shows the timing diagram required for
parallel output operations. In this diagram, only the I, Q and
Frequency data are taken from each sample before
incrementing to the next sample. Figure 39 assumes that the
pointer has already been incremented into a sample.
NOTE: For the very first sample read, the pointer must be
Figure 38 shows INTRRP going low before the FIFO is read.
The FIFO can be read before the number of samples
reaches the INTRRP pointer. The number of samples in the
FIFO must be monitored by the user via a status read.
FIGURE 38. INTERFACE BETWEEN A 16-BIT
incremented first and 4 PROCCLKs must pass before
this sample can be read.
PDC
MICROPROCESSOR AND PDC IN FIFO BUFFER
AOUT(7:0)
BOUT(7:0)
SEL(2:0)
INTRRP
OEAL
OEBL
39
INT
RD
D(15:8)
D(7:0)
A(2:0)
16-BIT
μP
HSP50214B
Suppose the depth of the Buffer RAM Output Section is
programmed for an INTRRP pointer depth of 4. If the output
is at 4 times the baud rate, the processing routine for the
microprocessor may only need to read the buffer when the
Buffer RAM had 4 samples since processing is usually on a
baud by baud basis.
Figure 39 illustrates the conceptual view of the FIFO as a
circular buffer, with the Write address one step ahead of the
Read Address.
Figure 40A deals with clockwise read and write address
incrementing. The FIFO depth is the difference between the
Write and Read pointers, modulo 8. Figure 40B illustrates a
FIFO status of Full, while Figure 40C illustrates a FIFO
empty status condition. Figure 40D illustrates a programmed
FIFO depth of 3 and the INTRRP signal indicating that the
buffer has sufficient data to be read.
Following some simple rules for operating the FIFO will
eliminate most operational errors:
Rule #1: The Read and Write Pointers cannot point at the
same address (the circuitry will not allow this).
Rule #2: The FIFO is full when the Write Address = Read
Address -1 (no more data will be written until some samples
are read or the FIFO is reset).
Rule #3: The FIFO is empty when the Read Address =
(Write Address -1) (the circuitry will not allow the read
pointer to be incremented).
Rule #4: You cannot write over what you have not read.
Rule #5: RESET places the Write address pointer = 000 and
Read address pointer = 111.
Rule #6: The best addressing scheme is to read the FIFO
until it is empty. This avoids erroneous INTRRP assertions
and provides for simple FIFO depth monitoring. The interrupt
is generated when the depth increments past the threshold.
AOUT(7:0),
BOUT(7:0)
PROCCLK
FIGURE 39. TIMING DIAGRAM FOR PDC IN FIFO MODE WITH
SEL(0:2)
INTRRP
OEAL,
OEBL
1 2 3 4
OUTPUTS I, Q, AND FREQUENCY SENT TO
AOUT(7:0) AND BOUT(7:0)
8 CLKS
0
I
5 6 7 8
Q
1
FR
4
7
> 4 CLKS
1 2 3 4
0
I
1
Q
May 1, 2007
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