HSP50214BVI Intersil, HSP50214BVI Datasheet - Page 55

• Manufacturer Part Number: HSP50214BVI
• Manufacturer: Intersil

Specifications of HSP50214BVI

• Lead Free Status / RoHS Status: Not Compliant

POSITION
BIT
N/A
CONTROL WORD 25: COUNTER AND ACCUMULATOR RESET (SYNCHRONIZED TO BOTH CLKIN AND PROCCLK)
Counter and
Accumulator Reset
FUNCTION
55
A write to this address initializes the counters and accumulators for testing. Items that are reset are:
Carrier NCO.
CIC Filter
Halfband Filters
255 Tap FIR
AGC Loop
Re-Sampler and Interpolation Halfband Filters.
Timing NCO
Discriminator
Cartesian to Polar Coordinate Counter
FIFO Control
Snapshot Control
Output Serial Control
1. Loads phase offset <9:0> into register to be used for adding to accumulator.
2. Enables feedback on the accumulator.
1. Resets the decimation counter.
2. Clears enables to CIC.
3. Clears accumulators in CIC.
4. Clears enable leaving CIC.
1. Resets compute counter in Halfband control.
2. Resets read address for all Halfband Filters.
3. Resets write address for all Halfband Filters.
4. Clears input available strobe.
5. Resets Halfband control logic.
1. Resets FIR read and write address pointers.
2. Zero’s coefficient read address.
1. Clears accumulator in loop filter.
1. Resets counters for Halfband addresses for writing.
2. Resets output enable.
3. Reset controller for Re-Sampler.
1. Initializes counters for inserting extra pulses when interpolating halfbands are enabled. In the
1. Resets read and write address pointers.
2. Zero’s coefficient read address.
1. Resets Cordic counters (stops current computation).
1. Resets decoder for controlling FIFO.
2. Resets write address for FIFO.
3. Clears RD and INTRRPT.
4. Resets “depth” and “full” flags.
5. Sets the empty flag.
6. Sets the read address to “7”, write address to “0”.
1. Zeros the group number.
2. Load interval counter.
3. Resets write address and read address for FIFO.
1. Reloads shift counter.
2. Reloads “Number of Words” counter.
3. Reloads counter for sync (for early or late).
4. Reloads counter for dividing down SERCLK.
5. In the HSP50214B, the Control Word 25 reset signal is designed such that the front end reset is 10
HSP50214B, a configuration control word bit determines if a Timing NCO reset is executed. If
Control Word 27, Bit 20 is set to a logic one, a reset will clear the feedback in the timing NCO phase
accumulator. If Control Word 27, Bit 20 is zero, a reset will not clear the timing NCO phase
accumulator feedback, which is how the HSP50214 operated.
CLKIN periods wide and the back end reset is 10 PROCCLK periods wide. This guarantees that no
enables will be caught in the pipelines.
HSP50214B
DESCRIPTION
May 1, 2007
FN4450.4