HSP50214BVI Intersil, HSP50214BVI Datasheet - Page 43

• Manufacturer Part Number: HSP50214BVI
• Manufacturer: Intersil

Specifications of HSP50214BVI

• Lead Free Status / RoHS Status: Not Compliant

Microprocessor Read Section
The microprocessor read uses both read and write
procedures to obtain data from the PDC. A write must be
done to location 5 to select the source of data to be read.
The read source is determined by the value placed on the
lower three bits of C(7:0). The output from a particular read
code is selected using a read address placed on A(2:0). The
output is sent to C(7:0) on the falling edge of RD.
If the Read Address is equal to 111, the Read Code is
ignored, and the status bits shown in Table 22 in the Output
Section is sent to C(7:0). This state was provided so that the
user could obtain the status bits quickly.
Refer to the Timing Diagram in Figure 46. Suppose the input
level detector has a hex value of (321AF5)H, then Table 21
details the steps to be taken.
(PROCCLK,
A2-0
C7-0
FIGURE 45. LOADING THE CONTROL REGISTERS WITH
STEP
WR
TABLE 20. EXAMPLE PROCESSOR WRITE SEQUENCE
1
2
3
4
5
6
CLKIN)
CLK =
LSB
CONFIGURATION
0
A(2:0)
000
001
010
100
011
32-BIT CONTROL WORDS
1
LOAD
DATA
2
0011 1000 Loads 38 into Master Register
1101 0000 Loads D0 into Master Register
0001 1000 Loads 18 into Master Register
0000 0000 Loads 00 into Master Register
0000 0000 Load
C(7:0)
MSB ADD
3
4
43
LOAD ADDRESS OF
TARGET CONTROL
(7:0) on rising edge of WR.
(15:8) on rising edge of WR.
(23:16) on rising edge of WR.
(31:24) on rising edge of WR.
Configuration Control Register 0.
Wait 4 CLKS.
REGISTER AND
WAIT 4 CLKs
1
2
COMMENT
“0018D038”
3
4
LOAD NEXT
REGISTER
0
URATION
CONFIG-
2
HSP50214B
into
PROCLK
TABLE 21. PROCESSOR READ SEQUENCE (INPUT LEVEL
CODE C(2:0)
STEP
FIGURE 46. READING THE CONTROL REGISTERS USING A
CONTROL REGISTER
A2-0
C7-0
1
2
3
4
LOAD ADDRESS
WR
READ
RD
000
001
010
100
011
OF TARGET
TABLE 22. DEFINITION OF ADDRESS MAP
A(2:0)
101
000
001
010
SELECTOR)
READ CODE C(2:0)
LATCH CODE EQUAL TO A 5, A READ ADDRESS
AND A READ CODE
Buffer RAM
I and Q
Buffer RAM
Output
(|r| and φ)
Buffered
Frequency
Not Used
Input Level
Detector
5
STATUS
TYPE
0001 1010
0011 0010
1111 1000
C(7:0)
(F4)H
(1A)H
(32)H
100
THREE-STATE
INPUT BUS
000- I LSB.
001- I MSB.
010- Q LSB.
011- Q MSB.
See Output Section.
000- MAG LSB (7-0).
001- MAG MSB (15-8).
010- PHASE LSB (7-0).
011- PHASE MSB (15-8).
See Output Section.
000- FREQ LSB.
001- FREQ MSB.
See Output Section.
Input AGC
000- input AGC LSB (0-7).
001- input AGC NLSB (8-15).
010- input AGC MSB (16-23).
READ ADDRESS
Write
Address 5, WR pulled high to
generate rising edge.
Drop RD low, Read AGC LSB.
Pull RD high, then drop low,
Read AGC NLSB.
Pull RD high, then drop low,
Read AGC MSB.
READ ADDRESS A(2:0)
TO ENABLE DATA
Read
OUTPUT ON C0-7
OUTPUT DATA C(7:0)
COMMENT
ASSERT RD
Code,
May 1, 2007
100
FN4450.4
to