HSP50214BVI Intersil, HSP50214BVI Datasheet - Page 40

• Manufacturer Part Number: HSP50214BVI
• Manufacturer: Intersil

Specifications of HSP50214BVI

• Lead Free Status / RoHS Status: Not Compliant

FIGURE 40D. FIFO READY IS WHEN (WRITE - READ) > DEPTH
FIGURE 40C. FIFO EMPTY IS WHEN (WRITE - READ) = 1
FIGURE 40B. FIFO FULL IS WHEN (WRITE - READ) = 7
FIGURE 40A. FIFO DEPTH IS (WRITE - READ
WRITE
5
4
5
4
5
4
5
4
FIGURE 40.
6
3
6
3
6
3
6
3
40
7
2
7
2
7
2
7
2
0
1
0
1
0
1
READY
0
1
READ
WRITE
DEPTH
WRITE
READ
FIFO
WRITE
READ
)
HSP50214B
FIFO Operation Via 8-Bit μProcessor
Interface
The Buffer RAM Output may also be accessed via the 8-bit
microprocessor interface C(7:0). Figure 41 shows the
conceptual configuration of the 8-bit μprocessor interface.
Control Word 20, Bit 24 must be set to 0 in order to obtain
Buffer RAM data to this output. The Microprocessor Read
Section describes how to read the data from each sample
out of the C(7:0) interface.
Recall that INTRRP stays low for 8 PROCCLK cycles. The
FIFO can be read before the INTRRP signal goes low; the
number of samples in the FIFO must be monitored by the user.
The timing relationship of the INTRRP to the snapshot data is
shown in Figure 42.
The read pointer of the FIFO is incremented when Control
Word 23 is written to. The data cannot be read from the
next sample until 4 PROCCLKs after the Buffer RAM
pointer has been incremented. Control Word 22 is used to
reset the Read and Write pointers of the Buffer RAM output
to the first sample to 000 and 007 for write and read
respectively.
May 1, 2007
FN4450.4