HSP50214BVI Intersil, HSP50214BVI Datasheet - Page 47

• Manufacturer Part Number: HSP50214BVI
• Manufacturer: Intersil

Specifications of HSP50214BVI

• Lead Free Status / RoHS Status: Not Compliant

Configuration Control Word Definitions
Note that in the Configuration Control Register Tables, some
of the available 32-bits in a Control Word are not used.
Unused bits do not need to be written to the Master Register.
If the destination only has 16-bits, then only 2 bytes need to
be written to the Master Register. Figure 45 details the timing
POSITION
31-21
16-13
12-7
BIT
5-4
20
19
18
17
6
3
2
1
0
Reserved
Carrier NCO External
Sync Enable
CIC External Sync
Enable
Input Format
Input Mode
CIC Shift Gain
CIC Decimation
Counter Preload
CIC Bypassed
Number of Offset
Frequency Bits
Syncout CLK Select
Clear Phase Accum
Carrier NCO Offset
Frequency Enable
Carrier NCO Load
Phase Accum On
Update
CONTROL WORD 0: CHIP CONFIGURATION, INPUT SECTION, CIC GAIN (SYNCHRONOUS TO CLKIN)
FUNCTION
47
Reserved.
0- The SYNCIN1 pin has no effect on the Carrier NCO.
1- When the SYNCIN1 pin is asserted, the carrier center frequency and phase are updated from the
holding registers to the active register. Also, if bit 0 of this word is active, the carrier phase accumulator
feedback will be zeroed to set the Carrier NCO to a known phase, allowing the NCOs of multiple parts
to be initialized and updated synchronously.
0- The SYNCIN1 pin has no effect on the CIC filter.
1- When the SYNCIN1 pin is asserted, the decimation counter is loaded, allowing the decimation
counters in multiple chips to be synchronized. When CW27 bit-22 is set to a 1, SYNCIN1 will reset both
front end and back end circuitry.
0- Two’s Complement Input Format.
1- Offset Binary Input Format.
0- Input operates in Gated Mode.
1- Input operates in Interpolated Mode.
These bits control the barrel shifter at the input to the CIC filter. These bits are added to the
GAINADJ(2:0) pins to determine the total shift. The sum is saturated at 15. See the CIC Decimation Filter
Section for values to be programmed in this field based on CIC filter Decimation. Bit 16 is the MSB.
SG = Floor [39 - (number of input bits) - 5log
SG = 15 for R = 4.
SG = 0 for R = 32.
These bits control the decimation in the CIC filter. Program this field to R-1, where R is the desired
decimation factor in the filter. The decimation factor range is 4-32. See CIC Filter Section for effective
decimation range relative to the CIC Shift Gain value. Bit 12 is the MSB.
While this field allows values from 0 - 63, the valid values are in the range from 4- 32.
Active high, this bit routes the output of the input shifter to the output of the CIC with no filtering.
When the CIC filter is bypassed, CLKIN must be at least twice the input sample rate (ENI should be
toggled to achieve this). When the CIC filter is bypassed, the bottom 24-bits of the barrel shifter output
are routed to the halfband filters.
00 - 8-bits.
01 - 16.
10 - 24.
11 - 32.
This bit selects whether the SYNCOUT signal is generated from CLKIN of from PROCCLK
0- CLKIN.
1- PROCLK.
0- Enable accumulator in Carrier NCO.
1- Zero feedback in accumulator.
When set to 1, this bit enables the offset frequency word to be added to the center frequency Control
Word. The offset is loaded serially via the COF and COFSYNC pins.
When this bit is set to 1, the μP update to the Carrier NCO frequency or an external carrier NCO load
using SYNCIN1 will zero the feedback of the phase accumulator, as well as update the phase or
frequency. This function can be used to set the NCO to a known phase synchronized to an external
event.
HSP50214B
for proper operation of the Microprocessor Write Section. Bits
identified as “Reserved” should be programmed to a zero.
NOTE: CLKIN or PROCCLK must be present to properly load
control words. Note in the header which is applicable.
DESCRIPTION
2
(R)] for 4 < R < 31
May 1, 2007
FN4450.4