HSP50214BVI Intersil, HSP50214BVI Datasheet - Page 31

• Manufacturer Part Number: HSP50214BVI
• Manufacturer: Intersil

Specifications of HSP50214BVI

• Lead Free Status / RoHS Status: Not Compliant

One caveat to selecting the FIR outputs to be routed directly
to the coordinate converter is that because the I/Q samples
for the coordinate conversion are chosen from before the
resampler, the magnitude and phase samples will not align
with the I/Q samples, if the resampler or interpolation
halfband filters are used.
This optional signal routing mode was intended for FM or for
burst PSK where a fixed decimation can be used. It is also
applicable when resampling or timing adjustments on the
demodulated samples are done in a processor following
PDC.
The magnitude resolution may suffer because there is no
gain adjustment before computing the magnitude. If the
signal is < - 90dBFS, it will be below the LSB of the
magnitude output.
The enable signal for gating data into the coordinate
converter is either the AGC data ready signal or the
resampler data ready signal. If the resampler is bypassed,
the AGC data ready signal is used and there is a delay of 6
clock cycles between the FIR data being ready and the
coordinate converter block sampling it. If the resampler is
enabled, its data ready signal will be delayed by 6 clocks (for
the AGC) plus the compute delay of the resampler block.
This may cause the I/Q to |r|/θ output sample alignment to
shift with decimation. For this reason, it is recommended that
the resampler/halfband filter block be bypassed when using
this new data path.
To select the output of the 255 tap programmable FIR filter to
be routed to the coordinate converter, set Control Word 27,
Bit 13 to a logic one. For routing as in the HSP50214, set
Control Word 27, Bit 13 to a logic zero.
Frequency Discriminator
The discriminator block delays phase from the Cartesian to
Polar Section and subtracts it from the latest sample. This
delay and subtract can be modeled as a programmable
delay comb filter. The output of the filter is dθ/dt, or
frequency. The transfer function of the discriminator is
set by
where D is the programmable discriminator delay expressed
in number of sample clock delays. The discriminator output
frequency is then filtered with a programmable FIR filter. The
Block Diagram of the Frequency Discriminator is shown in
Figure 29.
The range of delay in the discriminator is from 1 to 8
samples. Modulo 2π subtraction eliminates rollover problems
in the subtraction at 2π. The alias free discriminator
frequency range is given by:
Range
H z ( )
=
FREQDISC
1 Z
–
–
D
=
CW
±
F
SAMPOUT
31
⁄
(
D
+
1
)
;
(EQ. 21)
(EQ. 22)
HSP50214B
where D is the discriminator delay defined in Equation 21
(1 < D < 8), f
sample rate and CW is the desired center frequency. When
the phase multiplier is set to a value other than 2
discriminator range is reduced proportionally. The phase
multiplier can be 1, 2, 4 or 8 (2
reduces the range by 2, a multiply of 2
by 4, and a multiply of 2
The FIR filter can be configured with up to 63 symmetric taps
and up to 32 asymmetric taps. In the symmetric mode, the
FIR can be configured for even or odd symmetry, as well as
with an even or odd number of filter taps. Decimation is
provided to allow more processing time for longer (i.e., more
taps) filter structures.
†
The HSP50214B offers an expanded choice of signals to be
filtered by the discriminator FIR. The choices are:
1) 18-bits of delayed, and subtracted (and optionally shifted)
phase. This is the Discriminator FIR filter input found in the
HSP50214.
2) 18-bits of magnitude from the coordinate converter block.
This was added to provide for post-detection filtering of AM
signals.
3) 18-bits from the I output of the resampler/interpolation
halfband filter block. This was added to provide for
processing of SSB signals.
The shift, delay, and subtract functions are bypassed for
items (2) and (3).
In addition to the FIR input selections, the Q input to the
coordinate converter block can be zeroed so that the
magnitude output is the magnitude of I only. Again this was
added to provide for processing SSB signals.
FIGURE 29. FREQUENCY DISCRIMINATOR BLOCK DIAGRAM
Controlled via microprocessor interface.
DISCRIMINATOR DELAY
DISC. FIR DECIMATION
FIR SYMMETRY TYPE
PHASE MULTIPLIER
DISCRIMINATOR EN
FIR COEFFICIENTS
PHASE INPUT
FIR SYMMETRY
SAMPOUT
FIR TAPS
is the Discriminator FIR filter output
†
†
†
†
†
†
†
†
3
reduces the range by 8.
0
DELAY
63-TAP
FILTER
-
to 2
(1-8)
FIR
+
3
). Thus, a multiply of 2
+
2
reduces the range
FREQ(15:0)
(2’s COMPLEMENT)
0
, the
May 1, 2007
FN4450.4
1