HSP50214BVI Intersil, HSP50214BVI Datasheet - Page 38

• Manufacturer Part Number: HSP50214BVI
• Manufacturer: Intersil

Specifications of HSP50214BVI

• Lead Free Status / RoHS Status: Not Compliant

The FIFO mode allows the processor to service the interface
only when enough samples are present in the RAM. This
mode is provided so that the μProcessor does not have to
service the PDC every output sample. An interrupt,
INTRRPT, is asserted when the desired number of samples
are available. The PDC can be programmed to assert the
interrupt when up to 7 samples are available. Control Word
21, Bit 15 is used to set the Buffer RAM controller to the
FIFO mode, while Control Word 21, Bits 12-14 set the
number of RAM samples to be stored (0 to 7) before the
interrupt (INTRRPT) is asserted. Control Word 20, Bit 24
determines whether the RAM output interface is the 8-bit
microprocessor interface or the 16-bit processor interface. In
the 16-bit interface the MSByte is sent to AOUT(7:0) while
the LSByte is sent to BOUT(7:0).
The INTRRP output signal goes low for 8 PROCCLK cycles
when the number of samples in the Buffer RAM (depth)
reaches the programmed depth. The depth of the RAM is
calculated using Equation 23. A DSP microprocessor or the
data processing engine can use the INTRRP signal to know
that the RAM is ready to be read.
FIFO Operation Via 16-Bit μProcessor
Interface
Figure 37 shows the conceptual configuration of the 16-bit
μProcessor interface. This interface looks like a 16-bit
μProcessor read-only microprocessor interface. The
SEL(2:0) lines are the address bus and the OEAL and OEBL
lines are the read lines. The address is decoded as shown in
Table 17.
Use of the 16-bit interface for Buffer RAM output requires
Control Word 20, Bit 25, to be set to a logic “0” and Control
Word 20, Bit 24, to be set to a logic “1”. Once the Control
Word 20 has been set to route data to AOUT(7:0) and
BOUT(7:0), then the microprocessor must place a value on
the PDC input pins SEL(2:0), to choose which data type will
be output on AOUT(7:0) and 6BOUT(7:0). Table 17 defines
the data types in terms of SEL(2:0). With the control lines
set, the selected data is read MSByte on AOUT(7:0) and
LSByte on BOUT(7:0) when OEAL and OEBL (are low).
New data only read when OEBL goes low, so use μP for 8-
bit modes. Programming SEL(2:0) = 110 outputs a 16-bit
status signal on AOUT and BOUT. The FIFO status includes
FULL, EMPTY, FIFO Depth, and READYB. These status
signals are defined in Table 18.
D
RAM
=
[
(
ADDR
WRITE
–
ADDR
38
READ
) 1 ]
–
MOD8
(EQ. 23)
HSP50214B
NOTE: In the Status output, BOUT(7:0) are all GND.
|r|
DATA
Q
φ
ƒ
NEW
I
SEQUENCER
FIGURE 37. 16-BIT MICROPROCESSOR INTERFACE BUFFER
TABLE 17. BUFFER RAM OUTPUT SELECT DEFINITIONS
LOCATION
AOUT BIT
WRITE
16
16
16
16
16
SEL(2:0)
(7:5)
1-0
4
3
2
000
001
010
100
101
011
110
111
TABLE 18. STATUS BIT DEFINITIONS
RAM MODE BLOCK DIAGRAM
“SET OF WORDS”
INCR
WR
FIFO depth - When in FIFO mode, these bits are
the current depth of the FIFO.
EMPTY - When in FIFO mode, the FIFO is
empty, and the read pointer cannot be
advanced. Active High.
FULL - When in FIFO mode, the FIFO is full, and
new samples will not be written.
Active High.
READYB - When in FIFO mode, the output
buffer has reached the programmed threshold.
In the snapshot mode, the programmed number
of samples have been taken. Active Low.
GND
SEQUENCER
PROCCLK
ADDRESS
DUAL
PORT
I Data
Q Data
Magnitude
Phase
Frequency
Unused
Memory Status
Reading this address increments to the next
sample set
RAM
INCR
RD
OUTPUT DATA TYPE
I
Q
|r|
φ
ƒ
STATUS
INFORMATION
0
1
2
3
4
6
May 1, 2007
OUTPUT
DATA
OEBL
SEL(2:0)
FN4450.4