HSP50214BVI Intersil, HSP50214BVI Datasheet - Page 56

• Manufacturer Part Number: HSP50214BVI
• Manufacturer: Intersil

Specifications of HSP50214BVI

• Lead Free Status / RoHS Status: Not Compliant

POSITION
(15:12)
POSITION
(11:5)
(5:0)
BIT
19 - 18
31-25
12-0
BIT
24
23
22
21
20
17
16
15
14
13
eeee - AGC Exponent
mmmmmmm - AGC Mantissa
000000 - Not Used
Reserved
RAM Test Enable
Input Level Detector
Counter Preload
Select
SYNCIN1 Reset
Control
Timing Error Input
Select
Timing NCO Reset
Control Select
Discriminator FIR
Input
Input Level Detector
Integration Start
Select
AGC Average
Control
AGC Clear Inhibit
Q Input to Coordinate
Converter (see bits 19
- 15)
Coordinate Converter
Input
Reserved
FUNCTION
FUNCTION
56
CONTROL WORD 26: LOAD AGC GAIN (SYNCHRONIZED TO PROCCLK)
CONTROL WORD 27: TEST REGISTER (SYNCHRONIZED TO CLKIN)
A fixed value of 0000 000 is loaded here for normal operation.
0 = Normal Operation; 1 = RAM Test Enabled. The B Version includes test circuitry for the ROM and RAM
blocks that was not present in the original release part. This circuitry must be disabled before loading the
coefficient RAM’s. This is done by setting bit 24 to zero.
Because the HSP50214 did not require a “write” to Control Word 27 and the HSP50214B does
require that Control Word 27, Bit 24 be set to zero for normal operation, software that was written
for the HSP50214 will require modification to work properly with the HSP50214B.
0 = The two LSB’s of the interpolation period preload are set to zero.
1 = The two LSB’s of the interpolation period preload are set to one.
0: SYNCIN1 causes only front end reset.
1: SYNCIN1 causes front end and back end resets.
0 = Operates as HSP50214.
1 = Corrects an error in the 4 LSB’s.
0 = Backend reset will not clear the timing NCO phase accumulator feedback.
1 = Backend reset clears the timing NCO phase accumulator.
00 = 18-bits of delayed and subtracted (optionally shifted) phase.
01 = 18-bits of magnitude from coordinate converter.
1X = 18-bits of resampler/halfband filer I output.
0 = No external sync control of input end detector start/restart of integration period.
1 = SYNCIN causes the input level detector to start/restart its integration period.
0: AGC settles to mean.
1: AGC settles to median.
When set to zero, this bit will clear the AGC loop filter accumulator on a SYNCIN2 assertion or a WRITE
to CW25.
When set to a one, a WRITE to CW25 will not clear the AGC loop filter accumulator.
0 = I and Q enabled to coordinate converter.
I = Q input to coordinate converter is zeroed.
0 = The Resampler HB filter output is routed to coordinate converter.
1 = The output of 255 tap FIR is routed to coordinate converter.
A fixed value 0 0010 0111 1000 [0278]hex is loaded here for normal operation.
A fixed value 0 0010 0111 1010 [027A]hex is loaded here for setting the Sin/Cos Generator outputs to
7FFF.
AGC LOAD. Writing to this location generates a strobe to load the AGC loop accumulator with bits
(15:5) to the master registers. These bits are loaded into the MSBs of the AGC loop filter accumulator.
Bits 15:12 are the exponent associated with the AGC gain shifter, while bits 11:5 are the mantissa
associated with the AGC multiplier. The weighting of the AGC mantissa is 01.mmmmmmm. When
considering Figure 23, the AGC Block Diagram, note the mux between the Register and the Limiter
in the AGC Loop filter. The AGC LOAD controls the mux. Normally the mux would select the limiter
output. When the AGC LOAD is asserted via the write command, the mux selects the Write Master
Registers for data input See Table 20, Figure 45 and the associated text of the data sheet for an
explanation of how data is loaded into the Master Registers for use internal to the part. Note that for
the AGC LOAD only the lower 16-bits require data be valid to ensure a proper write of an AGC Value
that will be loaded on write to CONTROL WORD 26.
HSP50214B
DESCRIPTION
DESCRIPTION
May 1, 2007
FN4450.4