M66291GP#201 Renesas Electronics America, M66291GP#201 Datasheet - Page 30

• Manufacturer Part Number: M66291GP#201
• Description: IC USB CONTROLLER GEN-PUR 48LQFP
• Manufacturer: Renesas Electronics America

Specifications of M66291GP#201

• Package / Case: 48-LQFP
• Mounting Type: Surface Mount
• Current - Supply: 30mA
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -20°C ~ 85°C
• Interface: Serial
• Controller Type: USB 2.0 Controller
• Lead Free Status / RoHS Status: Not Compliant

M 6 6 2 9 1 G P / H P
R e v 1 . 0 1
(2) RESM (Resume Interrupt) Bit (b14)
(3) SOFR (SOF Detect Interrupt) Bit (b13)
(4) DVST (Device State Transition Interrupt) Bit (b12)
Note : At SCKE bit = “0” when XCKE bit = “1 ” or XCKE bit = “0”.
This bit indicates the change of USB bus state.
This bit is set to “1” when the USB bus state is changed from suspended (DVST bits = “1xx”) to “J”->“K” or
“J”->“SE0” (resume interrupt occurs).
This bit is cleared to “0” by writing “0” (interrupt is cleared).
This bit is set to “1” and can be read out even if the clock is not supplied (Note). This bit can also be cleared by
writing “0”. In case the clock is not supplied, make sure to write “1” after writing “0” (no further interrupt will
be accepted).
This bit indicates that the SOF packet is received and the frame number is updated.
This bit is set to “1” when the SOF packet is received and the frame number is stored at the timing set by the
FMOD bit of the Isochronous Status Register (SOF detect interrupt occurs).
This bit is cleared to “0” by writing “0” (interrupt is cleared).
This bit indicates the transition of the device state.
This bit is set to “1” when the transition of device states takes place as follows (device state transition
interrupt occurs):
The Conditions that this bit indicates "1" depend on the URST, SADR, SCFG or SUSP bits.
This bit is cleared to “0” by writing “0” (interrupt is cleared).
The present device state can be confirmed by the DVSQ bits.
2 0 0 4 . 1 1 . 0 1
(A) USB bus reset detect (Arbitrary state -> Default state):
(B) “SET_ADDRESS” execute (Default state -> Address state):
(C) “SET CONFIGURATION” execute (Address state -> Configured state):
(D) Suspend detect (Powered/Default/Address/Configured state -> Suspended state):
When the SE0 state continues for 2.5 us or more in D+ and D- pins, the USB bus reset is detected,
causing this bit to be set to “1”.
This bit is set to “1” when the SET_ADDRESS request is detected as (a) and the response is made
by zero-length packet in status stage.
This bit is set to “1” when the requests below are detected and ACK is received after the response
is made through zero-length packet in status stage.
The suspended state is detected and this bit is set to“1” when the idle state continues for 3 ms or
more in D+ and D- pins.
p a g e 3 0 o f 1 2 2
(a) “SET_ADDRESS” request in case device address value in default state is not “0”:
(a) “SET_CONFIGURATION” request in case configuration value in address state is not “0”
(b) “SET_CONFIGURATION” request in case configuration value in configured state is “0”
In case the wValue in default state is “0”, this bit is not set to “1”. When this request is
received, the device address value is set to the USB_Address Register, irrespective of the
setting of this bit.