M66291GP#201 Renesas Electronics America, M66291GP#201 Datasheet - Page 61

• Manufacturer Part Number: M66291GP#201
• Description: IC USB CONTROLLER GEN-PUR 48LQFP
• Manufacturer: Renesas Electronics America

Specifications of M66291GP#201

• Package / Case: 48-LQFP
• Mounting Type: Surface Mount
• Current - Supply: 30mA
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -20°C ~ 85°C
• Interface: Serial
• Controller Type: USB 2.0 Controller
• Lead Free Status / RoHS Status: Not Compliant

M 6 6 2 9 1 G P / H P
2.30 SIE_FIFO Status Register
R e v 1 . 0 1
(1) TGL (Buffer Toggle) Bit (b13)
15~14
b15
10~0
SIE_FIFO Status Register (SIE_FIFO_STATUS)
13
12
11
0
-
-
b
This register is valid against the endpoint set by the CPU_EP bits.
This bit is valid against the endpoint set to the OUT buffer (EPi_DIR bit = “0”) and is used for continuous
transmit/receive mode (EPi_RWMD = “1”). Do not write “1” when set to the IN buffer (EPi_DIR bit = “1”)
When “1” is written to this bit, the SIE side buffer is forced to complete receiving. The buffer is toggled,
irrespective of the presence/absence of the CPU side buffer data (causing the SIE side buffer to complete
receiving and to get toggled, and the IVAL bit to set to “1”). Make sure that the buffer data in the CPU side are
not cleared.
Here, the EPB_RDY bit also is set to “1” (buffer ready interrupt occurs).
2 0 0 4 . 1 1 . 0 1
Note:
Note:
Reserved. Set it to “0”.
TGL
Buffer Toggle
SCLR
Buffer Clear
Sreq
SIE_FIFO Ready
SIE_DTLN
SIE_FIFO Receive Data Length
14
0
-
-
Refer to “3.2 FIFO Buffer” for CPU/SIE side.
Make sure that the response PID is set to NAK (EPi_PID bits = “00”) and the Sreq bit to “0” before writing “1” to
this bit.
TGL
13
0
-
-
p a g e 6 1 o f 1 2 2
SCLR
12
0
-
-
Bit name
Sreq
11
0
-
-
10
0
-
-
9
0
-
-
<When set to OUT buffer>
0 :
1 :
<When set to IN buffer>
0 :
1 :
<When set to OUT buffer>
0 :
1 :
<When set to IN buffer>
0 :
1 :
0 :
1 :
Receive data length of SIE internal FIFO
Write
Write
Write
8
0
-
-
Invalid (Ignored when written)
Forces the buffer to toggle in receive ready state to read
ready state
Invalid (Ignored when written)
Inhibited
Invalid
Inhibited
Invalid (Ignored when written)
Clears the buffer in transmit ready state
Enables to be write to TGL bit/SCLR bit
Disables to be write to TGL bit/SCLR bit
7
0
-
-
6
0
-
-
SIE_DTLN
Function
5
0
-
-
4
0
-
-
3
0
-
-
2
0
-
-
<H/W reset : H'0000>
<Address : H’46>
<USB bus reset : ->
<S/W reset : ->
1
0
-
-
R
0
0
0
b0
0
-
-
W
0
×
×