M66291GP#201 Renesas Electronics America, M66291GP#201 Datasheet - Page 56

• Manufacturer Part Number: M66291GP#201
• Description: IC USB CONTROLLER GEN-PUR 48LQFP
• Manufacturer: Renesas Electronics America

Specifications of M66291GP#201

• Package / Case: 48-LQFP
• Mounting Type: Surface Mount
• Current - Supply: 30mA
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -20°C ~ 85°C
• Interface: Serial
• Controller Type: USB 2.0 Controller
• Lead Free Status / RoHS Status: Not Compliant

M 6 6 2 9 1 G P / H P
2.28 CPU_FIFO Control Register
R e v 1 . 0 1
b15
10~0
CPU_FIFO Control Register (CPU_FIFO_CONTROL)
15
14
13
12
11
0
-
-
b
2 0 0 4 . 1 1 . 0 1
IDLY
Reserved. Set it to “0”.
IDLY
Isochronous Transmit Delay Set
IVAL
IN Buffer Set/OUT Buffer Status
BCLR
Buffer Clear
Creq
CPU_FIFO Ready
CPU_DTLN
CPU_FIFO Receive Data Length Register
14
0
-
-
IVAL
13
0
-
-
p a g e 5 6 o f 1 2 2
BCLR
12
0
-
-
Bit name
Creq
11
1
-
-
10
0
-
-
9
0
-
-
0 :
1 :
<When set to OUT buffer>
0:
1:
Invalid (Ignored when written)
<When set to IN buffer>
0 :
1 :
0 :
1 :
<When set to OUT buffer>
0 :
1 :
<When set to IN buffer>
0 :
1 :
0 :
1 :
Stores the receive data length (byte count)
Read
Write
Read
Write
Write
Write
8
0
-
-
Disable of IDLY function
Enable of IDLY function
Disables reading data from the buffer
Enables reading data from the buffer
Incomplete to write the data to buffer
Complete to write the data to buffer
Invalid (Ignored when written)
Complete to write the data to buffer
Invalid (Ignored when written)
Buffer clear (When the IVAL bit is set to "1")
Invalid (Ignored when written)
Buffer clear (When the IVAL bit is set to "0")
Enables accessing CPU_FIFO Data Register etc,
Disables accessing CPU_FIFO Data Register etc,
7
(Forced completion : Transmits short packet)
0
-
-
6
0
-
-
CPU_DTLN
Function
5
0
-
-
4
0
-
-
3
0
-
-
2
0
-
-
<H/W reset : H'0800>
<Address : H’42>
<USB bus reset : ->
<S/W reset : ->
1
0
-
-
R
0
0
b0
0
-
-
W
0
×
×