M66291GP#201 Renesas Electronics America, M66291GP#201 Datasheet - Page 67

• Manufacturer Part Number: M66291GP#201
• Description: IC USB CONTROLLER GEN-PUR 48LQFP
• Manufacturer: Renesas Electronics America

Specifications of M66291GP#201

• Package / Case: 48-LQFP
• Mounting Type: Surface Mount
• Current - Supply: 30mA
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -20°C ~ 85°C
• Interface: Serial
• Controller Type: USB 2.0 Controller
• Lead Free Status / RoHS Status: Not Compliant

M 6 6 2 9 1 G P / H P
2.32 Dn_FIFO Control Registers (n=0~1)
R e v 1 . 0 1
(1) TRCLR (Transaction Count Clear) Bit (b15)
(2) TREN (Transaction Count Enable) Bit (b14)
TRCLR TREN
b15
10~0
D0_FIFO Control Register (D0_FIFO_CONTROL)
D1_FIFO Control Register (D1_FIFO_CONTROL)
15
14
13
12
11
0
-
-
b
When written to “1”, this bit clears the value of the DMAn_Transaction Count Register.
The writing of “1” to this bit is not retained and is automatically cleared to “0”.
This bit sets the enable/disable of transaction count function.
Refer to “2.34 DMAn_Transaction Count Registers (n=0~1)”.
2 0 0 4 . 1 1 . 0 1
TRCLR
Transaction Count Clear
TREN
Transaction Count Enable
IVAL
IN Buffer Set/OUT Buffer Status
BCLR
Buffer Clear
Dreq
D_FIFO Ready
DMA_DTLN
D_FIFO Receive Data Length Register
14
0
-
-
IVAL
13
0
-
-
p a g e 6 7 o f 1 2 2
BCLR
12
0
-
-
Bit name
Dreq
11
1
-
-
10
0
-
-
9
0
-
-
0 :
1 :
0 :
1 :
<When set to OUT buffer>
0:
1:
Invalid (Ignored when written)
<When set to IN buffer>
0 :
1 :
0 :
1 :
<When set to OUT buffer>
0 :
1 :
<When set to IN buffer>
0 :
1 :
0 :
1 :
Stores the receive data length (byte count)
Write
Read
Write
Read
Write
Write
Write
8
0
-
-
Invalid (Ignored when written)
Clears the DMAn_Transaction Count Register
Disable of transaction count function
Enable of transaction count function
Disables the reading of data from the buffer
Enables the reading of data from the buffer
Incomplete to write the data to buffer
Complete to write the data to buffer
Invalid (Ignored when written)
Complete to write the data to buffer
Invalid (Ignored when written)
Buffer clear (When the IVAL bit is set to "1")
Invalid (Ignored when written)
Buffer clear
Enables to access Dn_FIFO Data Register
Disables to access Dn_FIFO Data Register
7
(Forced completion : Transmits short packet)
0
-
-
6
0
-
-
DMA_DTLN
Function
5
0
-
-
4
0
-
-
3
0
-
-
2
0
-
-
<H/W reset : H'0800>
<Address : H’4A>
<Address : H’52>
<USB bus reset : ->
<S/W reset : ->
1
0
-
-
R
0
0
b0
0
-
-
W
×
×