M66291GP#201 Renesas Electronics America, M66291GP#201 Datasheet - Page 32

• Manufacturer Part Number: M66291GP#201
• Description: IC USB CONTROLLER GEN-PUR 48LQFP
• Manufacturer: Renesas Electronics America

Specifications of M66291GP#201

• Package / Case: 48-LQFP
• Mounting Type: Surface Mount
• Current - Supply: 30mA
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -20°C ~ 85°C
• Interface: Serial
• Controller Type: USB 2.0 Controller
• Lead Free Status / RoHS Status: Not Compliant

M 6 6 2 9 1 G P / H P
R e v 1 . 0 1
(11) VALID (Setup Packet Detect) Bit (b3)
SET _CO NFIG URAT IO N excecution[ConfigurationValue=0]
This bit indicates that the setup token has been received.
When the setup token is completely received, this bit is set to “1”.
When this bit is set to “1”, the writing to EP0_PID/CCPL bits of EP0_FIFO Control Register is ignored.
At the time of receiving the setup token, the interrupt has not occurred (the interrupt occurs only after the
termination of setup stage).
This bit is cleared to “0” by writing “0”.
2 0 0 4 . 1 1 . 0 1
(W hen URST bit="1", DVST bit is set to "1")
Note : The URST , SADR, SCFG and SUSP bits (Interrupt Enable Register 0) in the parenthesis set enable/disable to set the DVST bit to "1" for the
(
W hen SCFG bit="1", DVST bit is set to "1")
corresponding stage transition. There is no bit to set enable/disable to set the RESM bit to "1".
The stage transition takes place even if these bits are inhibited to set to "1".
USB bus reset detection
(W hen URST bit="1", DVST bit is set to "1")
p a g e 3 2 o f 1 2 2
USB bus reset detection
(DVSQ bits ="000")
Figure 2.6 Device State Transition
(DVSQ bits="001")
(DVSQ bits="010")
(DVSQ bits="011")
Configured
Powered
Address
Default
state
state
state
state
SET_ADDRESS excecution
(W hen SADR bit="1", DVST bit is set to "1")
SET_CO NFIGURATION excecution[ConfigurationValue= 0]
(W hen SCFG bit="1", DVST bit is set to "1")
(W hen SUSP bit="1", DVST bit is set to "1")
(W hen SUSP bit="1", DVST bit is set to "1")
(W hen SUSP bit="1", DVST bit is set to "1")
(W hen SUSP bit="1", DVST bit is set to "1")
Resume (RESM bit is set to "1")
Resume (RESM bit is set to "1")
Resume (RESM bit is set to "1")
Resume (RESM bit is set to "1")
Suspend detection
Suspend detection
Suspend detection
Suspend detection
(DVSQ bits="100")
(DVSQ bits="101")
(DVSQ bits="110")
(DVSQ bits="111")
Suspended
Suspended
Suspended
Suspended
state
state
state
state
/