M66291GP#201 Renesas Electronics America, M66291GP#201 Datasheet - Page 77

• Manufacturer Part Number: M66291GP#201
• Description: IC USB CONTROLLER GEN-PUR 48LQFP
• Manufacturer: Renesas Electronics America

Specifications of M66291GP#201

• Package / Case: 48-LQFP
• Mounting Type: Surface Mount
• Current - Supply: 30mA
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -20°C ~ 85°C
• Interface: Serial
• Controller Type: USB 2.0 Controller
• Lead Free Status / RoHS Status: Not Compliant

M 6 6 2 9 1 G P / H P
R e v 1 . 0 1
(4) EPi_Buf_siz (Buffer Size) Bits (b11~b8)
(5) EPi_DBLB (Double Buffer Mode) Bit (b7)
These bits set the buffer size in 64-byte unit (Note).
When set to double buffer mode (EPi_DBLB bit = “1”), the buffer double in size set by these bits is used.
Set the values to these bits as follows:
Set in the manner as follows (single transmit/receive mode only) to write “1” to the IDLY bit at isochronous
transfer mode (set by EPi_TYP bits):
When set to IN buffer (EPi_DIR bit = “1”), if the integral multiples of the value set by the EPi_MXPS bits is set
to these bits, the zero-length packet can be added after all data are transmitted. For details, refer to the
setting of “1” to the EPi_NULMD bit.
This bit sets the single buffer mode/double buffer mode.
This bit is applicable to bulk/isochronous/interrupt transfers (set by the EPi_TYP bits).
When set to double buffer mode, 2 buffers of size set by the EPi_Buf_siz bits are secured and are allocated to
SIE side buffer and CPU side buffer.
2 0 0 4 . 1 1 . 0 1
Note:
Note:
Double buffer mode when set to OUT buffer (EPi_DIR bit = “0”)
Double buffer mode when set to IN buffer (EPi_DIR bit = “1”)
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The M66291 is equipped with 3 Kbytes FIFO buffer. The Maximum buffer size is 1024Bytes for an endpoint, and
the minimum one is 64Bytes.
Refer to “3.2 FIFO Buffer” for CPU/SIE side.
SIE side buffer:
CPU side buffer:
Buffer toggle condition (switching of SIE side buffer and CPU side buffer)
SIE side buffer:
CPU side buffer:
Buffer toggle condition (switching of SIE side buffer and CPU side buffer)
Continuous transmit/receive mode
Single transmit/receive mode
Single transmit/receive mode
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p a g e 7 7 o f 1 2 2
The data received by SIE can be written.
Can not be accessed by CPU/DMA.
Can not be accessed by SIE.
The received data can be read by CPU/DMA.
SIE side buffer receive completion and CPU side buffer read completion (empty)
The receive completion changes according to the single/continuous transmit/receive mode.
For details, refer to the “EPi_RWMD bit” and the “TGL bit”.
SIE can transmit the written data.
Can not be accessed by CPU/DMA.
Can not be accessed by SIE.
CPU/DMA can write the data for transmission.
CPU side buffer write completion and SIE side buffer transmit completion (empty)
The write and transmit completion changes according to the single/continuous
transmit/receive mode.
For details, refer to the “EPi_RWMD bit”.
: Value set by this register > Value set by the EPi_MXPS bits
: Value set by this register ≥ Value set by the EPi_MXPS bits
: Value set by this register > Value set by the EPi_MXPS bits