M66291GP#201 Renesas Electronics America, M66291GP#201 Datasheet - Page 42

• Manufacturer Part Number: M66291GP#201
• Description: IC USB CONTROLLER GEN-PUR 48LQFP
• Manufacturer: Renesas Electronics America

Specifications of M66291GP#201

• Package / Case: 48-LQFP
• Mounting Type: Surface Mount
• Current - Supply: 30mA
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -20°C ~ 85°C
• Interface: Serial
• Controller Type: USB 2.0 Controller
• Lead Free Status / RoHS Status: Not Compliant

M 6 6 2 9 1 G P / H P
2.20 Control Transfer Control Register
R e v 1 . 0 1
(1) CTRR (Control Read Transfer Continuous Transmit Mode) Bit (b15)
(2) Ctr_Rd_Buf_Nmb (Control Read Buffer Start Number) Bits (b13~b8)
CTRR
b15
13~8
Control Transfer Control Register (CONTROL_TRANSFER)
5~0
15
14
0
-
-
b
7
6
This bit sets the transmit mode at data stage of the control read transfer.
In case of single transmit mode, the transmit completes after transmitting one packet under the condition as
follows:
In case of continuous transmit mode, the transmit completes after transmitting several packets under the
condition as follows:
In case of single transmit mode, the writing completes under the conditions as follows:
In case of continuous transmit mode, the writing completes under the conditions as follows:
The setting conditions of the IVAL bit of the EP0_FIFO Control Register change due to this bit.
These bits set the beginning block number of the buffer to be used in control read transfer. The block number
is a number by dividing the FIFO buffer into 64 byte sections (Note 1).
When the mode is set to single transmit (CTRR bit = “0”), the blocks set by these bits only are used and, from
the following block, it is possible to set to the buffer of a different endpoint.
When the mode is set to continuous transmit (CTRR bit = “1”), the buffer equivalent to the size set by the
EP0_FIFO Continuous Transmit Data Length Register (max. 256 bytes) is used from the block numbers set by
these bits (Note 2).
2 0 0 4 . 1 1 . 0 1
Note 1: The M66291 is equipped with 3 Kbytes FIFO buffer and has blocks from H’0 to H’2F.
Note 2: Make sure that several endpoints do not get overlapped in the same buffer area.
CTRR
Control Read Transfer Continuous Transmit
Mode
Reserved. Set it to "0".
Ctr_Rd_Buf_Nmb
Control Read Buffer Start Number
CTRW
Control Write Transfer Continuous Receive
Mode
Reserved. Set it to “0”.
Ctr_Wr_Buf_Nmb
Control Write Buffer Start Number
14
0
-
-
•
•
•
•
•
•
Transmits the data equivalent to the size set by the EP0 Packet Size Register or transmits a short
packet by setting the IVAL bit to “1”.
Transmits the data equivalent to the size set by the EP0_FIFO Continuous Transmit Data Length
Register or transmits a short packet by setting the IVAL bit to “1”.
Writes the data equivalent to the size set by the EP0 Packet Size Register to the buffer
(The IVAL bit of the EP0_FIFO Control Register changed to “1”).
Writes “1” to the IVAL bit of the EP0_FIFO Control Register.
Writes the data equivalent to the size set by the EP0_FIFO Continuous Transmit Data Length
Register (The IVAL bit of the EP0_FIFO Control Register changed to “1”).
Writes “1” to the IVAL bit of the EP0_FIFO Control Register.
13
0
-
-
p a g e 4 2 o f 1 2 2
12
0
-
-
Bit name
Ctr_Rd_Buf_Nmb
11
0
-
-
10
0
-
-
9
0
-
-
0 :
1 :
The top block number for the Control Read buffer
0 :
1 :
The top block number for the Control Write buffer
8
0
-
-
Single transmit mode
Continuous transmit mode
Unit receive mode
Continuous receive mode
CTRW
7
0
-
-
6
0
-
-
Function
5
0
-
-
4
0
-
-
Ctr_Wr_Buf_Nmb
3
0
-
-
2
0
-
-
<H/W reset : H'0000>
<Address : H’28>
<USB bus reset : ->
<S/W reset :->
1
0
-
-
R
0
0
b0
0
-
-
W
0
0