CY8C5246AXI-038 Cypress Semiconductor Corp, CY8C5246AXI-038 Datasheet - Page 13

• Manufacturer Part Number: CY8C5246AXI-038
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY8C5246AXI-038

• Lead Free Status / RoHS Status: Compliant

“address fetch” TD that reads the target address location from
the peripheral and writes that value into a subsequent TD in the
chain. This modifies the TD chain on the fly. When the “address
fetch” TD completes it moves on to the next TD, which has the
new address information embedded in it. This TD then carries
out the data transfer with the address location required by the
external master.
4.3.4.6 Scatter Gather DMA
In the case of scatter gather DMA, there are multiple
noncontiguous sources or destinations that are required to
effectively carry out an overall DMA transaction. For example, a
packet may need to be transmitted off of the device and the
packet elements, including the header, payload, and trailer, exist
in various noncontiguous locations in memory. Scatter gather
DMA allows the segments to be concatenated together by using
multiple TDs in a chain. The chain gathers the data from the
multiple locations. A similar concept applies for the reception of
data onto the device. Certain parts of the received data may need
to be scattered to various locations in memory for software
processing convenience. Each TD in the chain specifies the
location for each discrete element in the chain.
4.3.4.7 Packet Queuing DMA
Packet queuing DMA is similar to scatter gather DMA but
specifically refers to packet protocols. With these protocols,
there may be separate configuration, data, and status phases
associated with sending or receiving a packet.
Table 4-5. Cortex-M3 Exceptions and Interrupts
Bit 0 of each exception vector indicates whether the exception is
executed using ARM or Thumb instructions. Because the
Cortex-M3 only supports Thumb instructions, this bit must
always be 1. The Cortex-M3 non maskable interrupt (NMI) input
can be routed to any pin, via the DSI, or disconnected from all
pins. See
page 36.
Document Number: 001-55034 Rev. *G
1
2
3
4
5
6
7 – 10
11
12
13
14
15
16 – 47
Exception
Number
“DSI Routing Interface Description”
Reset
NMI
Hard fault
MemManage
Bus fault
Usage fault
–
SVC
Debug monitor
–
PendSV
SYSTICK
IRQ
Exception Type
–3 (highest)
–2
–1
Programmable
Programmable
Programmable
–
Programmable
Programmable
–
Programmable
Programmable
Programmable
Priority
PRELIMINARY
section on
0x00
0x04
0x08
0x0C
0x10
0x14
0x18
0x1C – 0x28
0x2C
0x30
0x34
0x38
0x3C
0x40 – 0x3FC
Exception Table
Address Offset
For instance, to transmit a packet, a memory mapped
configuration register can be written inside a peripheral,
specifying the overall length of the ensuing data phase. The CPU
can set up this configuration information anywhere in system
memory and copy it with a simple TD to the peripheral. After the
configuration phase, a data phase TD (or a series of data phase
TDs) can begin (potentially using scatter gather). When the data
phase TD(s) finish, a status phase TD can be invoked that reads
some memory mapped status information from the peripheral
and copies it to a location in system memory specified by the
CPU for later inspection. Multiple sets of configuration, data, and
status phase “subchains” can be strung together to create larger
chains that transmit multiple packets in this way. A similar
concept exists in the opposite direction to receive the packets.
4.3.4.8 Nested DMA
One TD may modify another TD, as the TD configuration space
is memory mapped similar to any other peripheral. For example,
a first TD loads a second TD’s configuration and then calls the
second TD. The second TD moves data as required by the
application. When complete, the second TD calls the first TD,
which again updates the second TD’s configuration. This
process repeats as often as necessary.
4.4 Interrupt Controller
The Cortex-M3 NVIC supports 16 system exceptions and 32
interrupts from peripherals, as shown in
The Nested Vectored Interrupt Controller (NVIC) handles
interrupts from the peripherals, and passes the interrupt vectors
to the CPU. It is closely integrated with the CPU for low latency
interrupt handling. Features include:


32 interrupts. Multiple sources for each interrupt.
Configurable number of priority levels: from 3 to 8.
PSoC
Starting value of R13 / MSP
Reset
Non maskable interrupt
All classes of fault, when the corresponding fault handler
cannot be activated because it is currently disabled or
masked
Memory management fault, for example, instruction
fetch from a nonexecutable region
Error response received from the bus system; caused
by an instruction prefetch abort or data access error
Typically caused by invalid instructions or trying to
switch to ARM mode
Reserved
System service call via SVC instruction
Debug monitor
Reserved
Deferred request for system service
System tick timer
Peripheral interrupt request #0 – #31
®
5: CY8C52 Family Datasheet
Function
Table
4-5.
Page 13 of 85
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