CY8C5246AXI-038 Cypress Semiconductor Corp, CY8C5246AXI-038 Datasheet - Page 21

• Manufacturer Part Number: CY8C5246AXI-038
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY8C5246AXI-038

• Lead Free Status / RoHS Status: Compliant

6.2.1 Power Modes
PSoC 5 devices have four different power modes, as shown in
Table 6-2
easily provide required functionality and processing power while
simultaneously minimizing power consumption and maximizing
battery life in low power and portable devices.
PSoC 5 power modes, in order of decreasing power
consumption are:




Table 6-2. Power Modes
Table 6-3. Power Modes Wakeup Time and Power Consumption
Document Number: 001-55034 Rev. *G
Active
Alternate
Active
Sleep
Hibernate
Power Modes
Active
Alternate
Active
Sleep
Hibernate <100 µs
Active
Alternate Active
Sleep
Hibernate
Modes
Sleep
and
<15 µs
Wakeup
–
–
Table
Time
Primary mode of operation, all
peripherals available (program-
mable)
Similar to Active mode, and is
typically configured to have
fewer peripherals active to
reduce power. One possible
configuration is to turn off the
CPU and flash, and run periph-
erals at full speed
All subsystems automatically
disabled 
All subsystems automatically
disabled 
Lowest power consuming mode
with all peripherals and internal
regulators disabled, except
hibernate regulator is enabled
Configuration and memory
contents retained
6-3. The power modes allow a design to
2 mA
TBD
2 µA
300 nA
Current
(Typ)
Description
[9]
Yes
User
defined
No
No
Execution
Code
PRELIMINARY
All
All
I
None
Resources
2
Wakeup, reset,
manual register
entry
Manual register
entry
Manual register
entry
Manual register
entry
Entry Condition Wakeup Source
C
Digital
All
All
Comparator ILO/kHzECO
None
Resources
Analog
Any interrupt
Any interrupt
Comparator,
PICU, I
CTW, LVD
PICU
Active is the main processing mode. Its functionality is
configurable. Each power controllable subsystem is enabled or
disabled by using separate power configuration template
registers. In alternate active mode, fewer subsystems are
enabled, reducing power. In sleep mode most resources are
disabled regardless of the template settings. Sleep mode is
optimized to provide timed sleep intervals and Real Time Clock
functionality. The lowest power mode is hibernate, which retains
register and SRAM state, but no clocks, and allows wakeup only
from I/O pins.
between power modes.
PSoC
2
C, RTC,
All
All
None
Clock Sources
Available
®
Figure 6-5
5: CY8C52 Family Datasheet
Any (program-
mable)
Any (program-
mable)
ILO/kHzECO
Active Clocks
illustrates the allowable transitions
–
–
Comparator,
PICU, I
CTW, LVD
PICU
Wakeup Sources
2
C, RTC,
All regulators available.
Digital and analog
regulators can be disabled
if external regulation used.
All regulators available.
Digital and analog
regulators can be disabled
if external regulation used.
Both digital and analog
regulators buzzed. 
Digital and analog
regulators can be disabled
if external regulation used.
Only hibernate regulator
active.
Regulator
All
All
XRES, LVD,
WDR
XRES
Sources
Reset
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