CY8C5246AXI-038 Cypress Semiconductor Corp, CY8C5246AXI-038 Datasheet - Page 5

• Manufacturer Part Number: CY8C5246AXI-038
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY8C5246AXI-038

• Lead Free Status / RoHS Status: Compliant

The details of the PSoC power modes are covered in the
System”
PSoC uses JTAG (4-wire) or SWD (2-wire) interfaces for
programming, debug, and test. Using these standard interfaces
enables the designer to debug or program the PSoC with a
variety of hardware solutions from Cypress or third party
vendors. The Cortex-M3 debug and trace modules include FPB,
DWT, ETM, and ITM. These modules have many features to help
solve difficult debug and trace problems. Details of the
programming, test, and debugging interfaces are discussed in
the
page 46 of this datasheet.
Document Number: 001-55034 Rev. *G
Note
3. Pins are No Connect (NC) on devices without USB. NC means that the pin has no electrical connection. The pin can be left floating or tied to a supply voltage or ground.
“Programming, Debug Interfaces, Resources”
section on page 20 of this datasheet.
(OpAmp0-/Extref0, GPIO) P0[3]
(TRACEDATA[0], GPIO) P2[4]
(TRACEDATA[1], GPIO) P2[5]
(TRACEDATA[2], GPIO) P2[6]
(TRACEDATA[3], GPIO) P2[7]
(OpAmp2out, GPIO) P0[0]
(OpAmp0out, GPIO) P0[1]
(TRACECLK, GPIO) P2[3]
(OpAmp0+, GPIO) P0[2]
(OpAmp2+, GPIO) P0[4]
(OpAmp2-, GPIO) P0[5]
(IDAC0, GPIO) P0[6]
(IDAC2, GPIO) P0[7]
(SIO) P12[2]
(SIO) P12[3]
PRELIMINARY
Figure 2-1. 48-pin SSOP Part Pinout
Vddio0
Vddio2
Vboost
Vddd
Vccd
Vssd
Vssb
Vbat
section on
Ind
10
11
12
13
15
17
18
19
20
21
22
23
24
14
16
“Power
5
8
1
2
3
4
6
7
9
Lines show
Vddio to I/O
supply
association
SSOP
2. Pinouts
The Vddio pin that supplies a particular set of pins is indicated
by the black lines drawn on the pinout diagrams in
Figure
multiple interface voltage levels, eliminating the need for off-chip
level shifters. Each Vddio may sink up to 100 mA total to its
associated I/O pins. On the 68-pin and 100-pin devices each set
of Vddio associated pins may sink up to 100 mA. The 48 pin
device may sink up to 100 mA total for all Vddio0 plus Vddio2
associated I/O pins and 100 mA total for all Vddio1 plus Vddio3
associated I/O pins.
46
45
43
37
33
32
31
29
28
48
47
44
42
41
40
39
38
36
35
34
30
27
26
25
PSoC
Vdda
Vssa
Vcca
P15[3] (GPIO, kHz XTAL: Xi)
P15[2] (GPIO, kHz XTAL: Xo)
P12[1] (SIO, I2C1: SDA)
P12[0] (SIO, I2C1: SCL)
Vddio3
P15[1] (GPIO, MHz XTAL: Xi)
P15[0] (GPIO, MHz XTAL: Xo)
Vccd
Vssd
Vddd
P15[7] (USBIO, D-, SWDCK)
P15[6] (USBIO, D+, SWDIO)
P1[7] (GPIO)
P1[6] (GPIO)
Vddio1
P1[5] (GPIO, nTRST)
P1[4] (GPIO, TDI)
P1[3] (GPIO, TDO, SWV)
P1[2] (GPIO, configurable XRES)
P1[1] (GPIO, TCK, SWDCK)
P1[0] (GPIO, TMS, SWDIO)
2-3. Using the Vddio pins, a single PSoC can support
®
5: CY8C52 Family Datasheet
[3]
[5]
[5]
Figure 2-2
Page 5 of 85
and
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