CY8C5246AXI-038 Cypress Semiconductor Corp, CY8C5246AXI-038 Datasheet - Page 29

• Manufacturer Part Number: CY8C5246AXI-038
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY8C5246AXI-038

• Lead Free Status / RoHS Status: Compliant

6.4.11 Adjustable Output Level
This section applies only to SIO pins. SIO port pins support the
ability to provide a regulated high output level for interface to
external signals that are lower in voltage than the SIO’s
respective V
either the standard V
based on an internally generated reference. Typically the voltage
DAC (VDAC) is used to generate the reference. The
page 45 has more details on VDAC use and reference routing to
the SIO pins. Resistive pull up and pull down drive modes are
not available with SIO in regulated output mode.
6.4.12 Adjustable Input Level
This section applies only to SIO pins. SIO pins by default support
the standard CMOS and LVTTL input levels but also support a
differential mode with programmable levels. SIO pins are
grouped into pairs. Each pair shares a reference generator block
which, is used to set the digital input buffer reference level for
interface to external signals that differ in voltage from V
reference sets the pins voltage threshold for a high logic level.
Available input thresholds are:




Typically the voltage DAC (VDAC) generates the V
reference. The
and reference routing to the SIO pins.
6.4.13 SIO as Comparator
This section applies only to SIO pins. The adjustable input level
feature of the SIOs as explained in the
section can be used to construct a comparator. The threshold for
the comparator is provided by the SIO's reference generator. The
reference generator has the option to set the analog signal
routed through the analog global line as threshold for the
comparator. Note that a pair of SIO pins share the same
threshold.
The digital input path in
functionality. In the figure, ‘Reference level’ is the analog signal
routed through the analog global. The hysteresis feature can
also be enabled for the input buffer of the SIO, which increases
noise immunity for the comparator.
6.4.14 Hot Swap
This section applies only to SIO pins. SIO pins support ‘hot swap’
capability to plug into an application without loading the signals
that are connected to the SIO pins even when no power is
applied to the PSoC device. This allows the unpowered PSoC to
maintain a high impedance load to the external device while also
preventing the PSoC from being powered through a GPIO pin’s
protection diode.
6.4.15 Over Voltage Tolerance
All I/O pins provide an over voltage (V
tolerance feature at any operating V

Document Number: 001-55034 Rev. *G
0.5 V
0.4 V
0.5 V
V
There are no current limitations for the SIO pins as they present
a high impedance load to the external circuit.
REF
DDIO
DDIO
REF
DDIO
DAC
. SIO pins are individually configurable to output
on page 45 has more details on VDAC use
DDIO
Figure 6-9
level or the regulated output, which is
on page 26 illustrates this
DD
DDIO
.
Adjustable Input Level
< V
PRELIMINARY
IN
< V
REF
DDA
DAC
DDIO
)
. The
on


A common application for this feature is connection to a bus such
as I
voltages. In the I
Open Drain, Drives Low mode for the SIO pin. This allows an
external pull up to pull the I
supply. For example, the PSoC chip could operate at 1.8 V, and
an external device could run from 5 V. Note that the SIO pin’s V
and V
pin.
The I/O pin must be configured into a high impedance drive
mode, open drain low drive mode, or pull down drive mode, for
over voltage tolerance to work properly. Absolute maximum
ratings for the device must be observed for all I/O pins.
6.4.16 Reset Configuration
While reset is active all I/Os are reset to and held in the High
Impedance Analog state. After reset is released, the state can be
reprogrammed on a port-by-port basis to pull down or pull up. To
ensure correct reset operation, the port reset configuration data
is stored in special nonvolatile registers. The stored reset data is
automatically transferred to the port reset configuration registers
at reset release.
6.4.17 Low Power Functionality
In all low power modes the I/O pins retain their state until the part
is awakened and changed or reset. To awaken the part, use a
pin interrupt, because the port interrupt logic continues to
function in all low power modes.
6.4.18 Special Pin Functionality
Some pins on the device include additional special functionality
in addition to their GPIO or SIO functionality. The specific special
function pins are listed in
features are:


6.4.19 JTAG Boundary Scan
The device supports standard JTAG boundary scan chains on all
pins for board level test.
The GPIO pins must be limited to 100 µA using a current limiting
resistor. GPIO pins clamp the pin voltage to approximately one
diode above the V
In case of a GPIO pin configured for analog input/output, the
analog voltage on the pin must not exceed the V
voltage to which the GPIO belongs.
Digital







Analog


PSoC
2
4- to 33-MHz crystal oscillator
32.768-kHz crystal oscillator
Wake from sleep on I
for I
JTAG interface pins
SWD interface pins
SWV interface pins
External reset
High current IDAC output
External reference inputs
C where different devices are running from different supply
IL
2
levels are determined by the associated V
C if wake from sleep is not required.
®
5: CY8C52 Family Datasheet
2
C case, the PSoC chip is configured into the
DDIO
2
supply.
“Pinouts”
C address match. Any pin can be used
2
C bus voltage above the PSoC pin
on page 5. The special
DDIO
DDIO
Page 29 of 85
supply
supply
IH
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