MC9S12XDP512MAG Freescale, MC9S12XDP512MAG Datasheet - Page 138

• Manufacturer Part Number: MC9S12XDP512MAG
• Manufacturer: Freescale

Specifications of MC9S12XDP512MAG

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 40MHz
• Interface Type: CAN/I2C/SCI/SPI
• Total Internal Ram Size: 32KB
• # I/os (max): 119
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/3.15V
• On-chip Adc: 2(24-chx10-bit)
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

Chapter 4 Analog-to-Digital Converter (ATD10B16CV4) Block Description
4.3.2.5
This register selects the conversion clock frequency, the length of the second phase of the sample time and
the resolution of the A/D conversion (i.e., 8-bits or 10-bits). Writes to this register will abort current
conversion sequence but will not start a new sequence.
Read: Anytime
Write: Anytime
138
SMP[1:0]
PRS[4:0]
Reset
SRES8
Field
6:5
4:0
W
7
R
SRES8
ATD Control Register 4 (ATDCTL4)
0
7
A/D Resolution Select — This bit selects the resolution of A/D conversion results as either 8 or 10 bits. The
A/D converter has an accuracy of 10 bits. However, if low resolution is required, the conversion can be speeded
up by selecting 8-bit resolution.
0 10 bit resolution
1 8 bit resolution
Sample Time Select —These two bits select the length of the second phase of the sample time in units of ATD
conversion clock cycles. Note that the ATD conversion clock period is itself a function of the prescaler value
(bits PRS4-0). The sample time consists of two phases. The first phase is two ATD conversion clock cycles
long and transfers the sample quickly (via the buffer amplifier) onto the A/D machine’s storage node. The
second phase attaches the external analog signal directly to the storage node for final charging and high
accuracy.
ATD Clock Prescaler — These 5 bits are the binary value prescaler value PRS. The ATD conversion clock
Note: The maximum ATD conversion clock frequency is half the bus clock. The default (after reset) prescaler
frequency is calculated as follows:
value is 5 which results in a default ATD conversion clock frequency that is bus clock divided by 12.
Table 4-13
SMP1
Table 4-12
0
0
1
1
SMP1
0
6
ATDclock
illustrates the divide-by operation and the appropriate range of the bus clock.
Figure 4-7. ATD Control Register 4 (ATDCTL4)
lists the lengths available for the second sample phase.
Table 4-11. ATDCTL4 Field Descriptions
SMP0
MC9S12XDP512 Data Sheet, Rev. 2.21
SMP0
=
Table 4-12. Sample Time Select
0
1
0
1
0
5
------------------------------- -
BusClock
PRS
+
1
PRS4
0
4
Length of 2nd Phase of Sample Time
0.5
16 A/D conversion clock periods
Description
2 A/D conversion clock periods
4 A/D conversion clock periods
8 A/D conversion clock periods
PRS3
0
3
PRS2
1
2
Freescale Semiconductor
PRS1
0
1
PRS0
1
0