MC9S12XDP512MAG Freescale, MC9S12XDP512MAG Datasheet - Page 434

• Manufacturer Part Number: MC9S12XDP512MAG
• Manufacturer: Freescale

Specifications of MC9S12XDP512MAG

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 40MHz
• Interface Type: CAN/I2C/SCI/SPI
• Total Internal Ram Size: 32KB
• # I/os (max): 119
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/3.15V
• On-chip Adc: 2(24-chx10-bit)
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV3)
Read: Anytime
Write: Anytime for TXEx flags when not in initialization mode; write of 1 clears flag, write of 0 is ignored
10.3.2.8
This register contains the interrupt enable bits for the transmit buffer empty interrupt flags.
434
TXE[2:0]
Field
2:0
Reset:
Reset:
W
W
R
R
Transmitter Buffer Empty — This flag indicates that the associated transmit message buffer is empty, and thus
not scheduled for transmission. The CPU must clear the flag after a message is set up in the transmit buffer and
is due for transmission. The MSCAN sets the flag after the message is sent successfully. The flag is also set by
the MSCAN when the transmission request is successfully aborted due to a pending abort request (see
Section 10.3.2.9, “MSCAN Transmitter Message Abort Request Register
transmit interrupt is pending while this flag is set.
Clearing a TXEx flag also clears the corresponding ABTAKx (see
Message Abort Acknowledge Register
is cleared (see
When listen-mode is active (see
cannot be cleared and no transmission is started.
Read and write accesses to the transmit buffer will be blocked, if the corresponding TXEx bit is cleared
(TXEx = 0) and the buffer is scheduled for transmission.
0 The associated message buffer is full (loaded with a message due for transmission)
1 The associated message buffer is empty (not scheduled)
MSCAN Transmitter Interrupt Enable Register (CANTIER)
The CANTFLG register is held in the reset state when the initialization
mode is active (INITRQ = 1 and INITAK = 1). This register is writable when
not in initialization mode (INITRQ = 0 and INITAK = 0).
0
0
0
0
7
7
Figure 10-11. MSCAN Transmitter Interrupt Enable Register (CANTIER)
Figure 10-10. MSCAN Transmitter Flag Register (CANTFLG)
Section 10.3.2.9, “MSCAN Transmitter Message Abort Request Register
= Unimplemented
= Unimplemented
Table 10-11. CANTFLG Register Field Descriptions
0
0
0
0
6
6
MC9S12XDP512 Data Sheet, Rev. 2.21
Section 10.3.2.2, “MSCAN Control Register 1
0
0
0
0
5
5
(CANTAAK)”). When a TXEx flag is set, the corresponding ABTRQx bit
NOTE
0
0
0
0
4
4
Description
3
0
0
3
0
0
Section 10.3.2.10, “MSCAN Transmitter
TXEIE2
(CANTARQ)”). If not masked, a
TXE2
1
0
2
2
(CANCTL1)”) the TXEx flags
Freescale Semiconductor
TXEIE1
TXE1
(CANTARQ)”).
1
0
1
1
TXEIE0
TXE0
1
0
0
0