MC9S12XDP512MAG Freescale, MC9S12XDP512MAG Datasheet - Page 407

• Manufacturer Part Number: MC9S12XDP512MAG
• Manufacturer: Freescale

Specifications of MC9S12XDP512MAG

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 40MHz
• Interface Type: CAN/I2C/SCI/SPI
• Total Internal Ram Size: 32KB
• # I/os (max): 119
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/3.15V
• On-chip Adc: 2(24-chx10-bit)
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

from where was during the previous transmission. It is not possible for the IIC to wake up the CPU when
its internal clocks are stopped.
If it were the case that the IBSWAI bit was cleared when the WAI instruction was executed, the IIC internal
clocks and interface would remain alive, continuing the operation which was currently underway. It is also
possible to configure the IIC such that it will wake up the CPU via an interrupt at the conclusion of the
current operation. See the discussion on the IBIF and IBIE bits in the IBSR and IBCR, respectively.
9.3.2.4
This status register is read-only with exception of bit 1 (IBIF) and bit 4 (IBAL), which are software
clearable.
Freescale Semiconductor
RESERVED
Reset
Field
IAAS
IBAL
TCF
IBB
7
6
5
4
3
W
R
TCF
Data Transferring Bit — While one byte of data is being transferred, this bit is cleared. It is set by the falling
edge of the 9th clock of a byte transfer. Note that this bit is only valid during or immediately following a transfer
to the IIC module or from the IIC module.
0 Transfer in progress
1 Transfer complete
Addressed as a Slave Bit — When its own specific address (I-bus address register) is matched with the calling
address, this bit is set.The CPU is interrupted provided the IBIE is set.Then the CPU needs to check the SRW
bit and set its Tx/Rx mode accordingly.Writing to the I-bus control register clears this bit.
0 Not addressed
1 Addressed as a slave
Bus Busy Bit
0 This bit indicates the status of the bus. When a START signal is detected, the IBB is set. If a STOP signal is
1 Bus is busy
Arbitration Lost — The arbitration lost bit (IBAL) is set by hardware when the arbitration procedure is lost.
Arbitration is lost in the following circumstances:
This bit must be cleared by software, by writing a one to it. A write of 0 has no effect on this bit.
Reserved — Bit 3 of IBSR is reserved for future use. A read operation on this bit will return 0.
IIC Status Register (IBSR)
1
7
detected, IBB is cleared and the bus enters idle state.
1. SDA sampled low when the master drives a high during an address or data transmit cycle.
2. SDA sampled low when the master drives a high during the acknowledge bit of a data receive cycle.
3. A start cycle is attempted when the bus is busy.
4. A repeated start cycle is requested in slave mode.
5. A stop condition is detected when the master did not request it.
IAAS
= Unimplemented or Reserved
0
6
Figure 9-7. IIC Bus Status Register (IBSR)
Table 9-7. IBSR Field Descriptions
MC9S12XDP512 Data Sheet, Rev. 2.21
IBB
0
5
IBAL
0
4
Description
Chapter 9 Inter-Integrated Circuit (IICV2) Block Description
0
0
3
SRW
0
2
IBIF
0
1
RXAK
0
0
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