MC9S12XDP512MAG Freescale, MC9S12XDP512MAG Datasheet - Page 702

MC9S12XDP512MAG

Manufacturer Part Number
MC9S12XDP512MAG
Description
Manufacturer
Freescale
Datasheet

Specifications of MC9S12XDP512MAG

Cpu Family
HCS12
Device Core Size
16b
Frequency (max)
40MHz
Interface Type
CAN/I2C/SCI/SPI
Total Internal Ram Size
32KB
# I/os (max)
119
Number Of Timers - General Purpose
12
Operating Supply Voltage (typ)
2.5/5V
Operating Supply Voltage (max)
2.75/5.5V
Operating Supply Voltage (min)
2.35/3.15V
On-chip Adc
2(24-chx10-bit)
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 125C
Operating Temperature Classification
Automotive
Mounting
Surface Mount
Pin Count
144
Package Type
LQFP
Program Memory Type
Flash
Program Memory Size
512KB
Lead Free Status / RoHS Status
Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC9S12XDP512MAG
Manufacturer:
FREESCALE
Quantity:
5 530
Part Number:
MC9S12XDP512MAG
Manufacturer:
Exar
Quantity:
20
Part Number:
MC9S12XDP512MAG
Manufacturer:
FREESCALE
Quantity:
3 450
Part Number:
MC9S12XDP512MAG
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MC9S12XDP512MAG
Manufacturer:
FREESCALE
Quantity:
3 450
Chapter 19 S12X Debug (S12XDBGV2) Module
19.3.1.6
Read: Anytime
Write: Never
704
0x0026
CNT[6:0]
Reset
POR
Field
6–0
W
R
1
Count Value — The CNT bits [6:0] indicate the number of valid data 64-bit data lines stored in the trace buffer.
Table 19-18
When the CNT rolls over to 0, the TBF bit in DBGSR is set and incrementing of CNT will continue in end-trigger
or mid-trigger mode. The DBGCNT register is cleared when ARM in DBGC1 is written to a 1. The DBGCNT
register is cleared by power-on-reset initialization but is not cleared by other system resets. Thus should a reset
occur during a debug session, the DBGCNT register still indicates after the reset, the number of valid trace buffer
entries stored before the reset occurred. The DBGCNT register is not decremented when reading from the trace
buffer.
TBF (DBGSR)
This applies to normal/loop1 modes when tracing from either CPU or XGATE only.
Debug Count Register (DBGCNT)
0
0
0
7
0
0
0
0
0
1
1
Unimplemented or Reserved
shows the correlation between the CNT bits and the number of valid data lines in the trace buffer.
0
6
CNT[6:0]
0000000
0000001
0000010
0000011
0000100
0000110
1111100
1111110
0000000
0000010
1111110
Figure 19-9. Debug Count Register (DBGCNT)
Table 19-17. DBGCNT Field Descriptions
..
..
..
MC9S12XDP512 Data Sheet, Rev. 2.21
Table 19-18. CNT Decoding Table
0
5
oldest data has been overwritten by most recent data
ARM bit will be cleared and the tracing session ends.
64 lines valid; if using begin-trigger alignment,
0
4
Description
32 bits of one line valid
1.5 lines valid
64 lines valid,
CNT
No data valid
62 lines valid
63 lines valid
Description
2 lines valid
3 lines valid
1 line valid
0
3
..
1
0
2
1
Freescale Semiconductor
0
1
0
0

Related parts for MC9S12XDP512MAG