MC9S12DG128VPVE Freescale, MC9S12DG128VPVE Datasheet - Page 122

• Manufacturer Part Number: MC9S12DG128VPVE
• Manufacturer: Freescale

Specifications of MC9S12DG128VPVE

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 50MHz
• Interface Type: SCI/SPI/I2C/CAN
• Total Internal Ram Size: 8KB
• # I/os (max): 91
• Number Of Timers - General Purpose: 8
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.25V
• Operating Supply Voltage (min): 2.25/2.35/4.5V
• On-chip Adc: 2(8-chx10-bit)
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 105C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 112
• Package Type: LQFP
• Program Memory Type: Flash
• Program Memory Size: 128KB
• Lead Free Status / RoHS Status: Compliant

Device User Guide — 9S12DT128DGV2/D V02.16
The following procedure can be used to calculate the resistance and capacitance values using typical
values for K
The grey boxes show the calculation for f
for f
The VCO Gain at the desired VCO frequency is approximated by:
The phase detector relationship is given by:
i
The loop bandwidth f
typical values are 50. = 0.9 ensures a good transient response.
ch
122
is the current in tracking mode.
OSC
= 4MHz and a 25MHz bus clock.
1
, f
1
and i
f
osc
K
V
C
f
ch
C
should be chosen to fulfill the Gardner’s stability criteria by at least a factor of 10,
from (Table A-16).
=
<
K
refdv+1
K
------------------------------------------
Figure A-3 Basic PLL functional diagram
1
=
1
2
e
–
---------------------- -
+
f
K
i
1
ch
1
f
–
ref
VDDPLL
1
f
f
1V
ref
VCO
vco
+
K
=
V
= 50MHz and f
2
–
100
f
----- -
10
cmp
1
C
C
p
Loop Divider
s
e
Detector
= 316.7Hz/
----------------------- -
Phase
60 50
f
synr+1
C
f
K
–
C
100
ref
1
–
<
R
< 25kHz
= 1MHz. E.g., these frequencies are used
------------- -
4 10
= -90.48MHz/V
f
ref
;
XFC Pin
=
1
2
0.9
Freescale Semiconductor
VCO
K
V
f
vco