MC9S12DG128VPVE Freescale, MC9S12DG128VPVE Datasheet - Page 4

• Manufacturer Part Number: MC9S12DG128VPVE
• Manufacturer: Freescale

Specifications of MC9S12DG128VPVE

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 50MHz
• Interface Type: SCI/SPI/I2C/CAN
• Total Internal Ram Size: 8KB
• # I/os (max): 91
• Number Of Timers - General Purpose: 8
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.25V
• Operating Supply Voltage (min): 2.25/2.35/4.5V
• On-chip Adc: 2(8-chx10-bit)
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 105C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 112
• Package Type: LQFP
• Program Memory Type: Flash
• Program Memory Size: 128KB
• Lead Free Status / RoHS Status: Compliant

Device User Guide — 9S12DT128DGV2/D V02.16
Number
Version
V02.07
V02.08
V02.09
V02.10
V02.11
4
Revision
29 Jan
26 Feb
15 Oct
3 May
6 Feb
Date
2003
2003
2003
2004
2004
Effective
26 Feb
29 Jan
15 Oct
3 May
6 Feb
Date
2003
2003
2003
2004
2004
Author
Added 3L40K mask set in section 1.6
Corrected register entries in section 1.5.1 “Detailed Memory Map”
Updated description for ROMCTL in section 2.3.31
Updated section 4.3.3 “Unsecuring the Microcontroller”
Corrected and updated device-specific information for OSC
(section 8.1) & Byteflight (section 15.1)
Updated footnote in Table A-4 “Operating Conditions”
Changed reference of VDDM to VDDR in section A.1.8
Removed footnote on input leakage current in Table A-6 “5V I/O
Characteristics”
Added part numbers MC9S12DT128E, MC9S12DG128E, and
MC9S12DJ128E in “Preface” and related part number references
Removed mask sets 0L40K and 2L40K from Table 1-3
Replaced references to HCS12 Core Guide by the individual
HCS12 Block guides in Table 0-2, section 1.5.1, and section 6;
updated Fig.3-1 “Clock Connections” to show the individual HCS12
blocks
Corrected PIM module name and document order number in Table
0-2 “Document References”
Corrected ECT pulse accumulators description in section 1.2
“Features”
Corrected KWP5 pin name in Fig 2-1 112LQFP pin assignments
Corrected pull resistor CTRL/reset states for PE7 and PE4-PE0 in
Table 2.1 “Signal Properties”
Mentioned “S12LRAE” bootloader in Flash section 17
Corrected footnote on clamp of TEST pin under Table A-1
“Absolute Maximum Ratings”
Corrected minimum bus frequency to 0.25MHz in Table A-4
“Operating Conditions”
Replaced “burst programming” by “row programming” in A.3 “NVM,
Flash and EEPROM”
Corrected blank check time for EEPROM in Table A-11 “NVM
Timing Characteristics”
Corrected operating frequency in Table A-18 “SPI Master/Slave
Mode Timing Characteristics
Added A128 information in “Derivative Differences”, 2.1 “Device
Pinout”, 2.2 “Signal Properties Summary”, Fig 23-2 & Fig 23-4
Added lead-free package option (PVE) in Table 0-2 “Derivative
Differences for MC9S12DB128” and Fig 0-1 “Order Partnumber
Example”
Added an “AEC qualified” row in the “Derivative Differences” tables
0-1 & 0-2.
Added part numbers SC515846, SC515847, SC515848, and
SC515849 in “Derivative Differences” tables 0-1 & 0-2, section 2,
and section 23.
Corrected and added maskset 4L40K in tables 0-1 & 0-2 and
section 1.6.
Corrected BDLC module availability in DB128 80QFP part in
“Derivative Differences” table 0-2.
Description of Changes
Freescale Semiconductor