QG80333M500 S L9BH Intel, QG80333M500 S L9BH Datasheet - Page 22

• Manufacturer Part Number: QG80333M500 S L9BH
• Manufacturer: Intel

Specifications of QG80333M500 S L9BH

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Intel® 80333 I/O Processor
Non-Core Errata
24.
Problem:
Implication:
Workaround:
Status:
25.
Problem:
Implication:
Workaround:
Status:
26.
Problem:
Implication:
Workaround:
Status:
22
Performance across an upstream ×1 PCI Express* link is less than expected
When the 80333 is configured with an upstream ×1 PCI Express* link, the realized performance is
significantly less than the predicted linear assumption that a x1 link provides 1/4 the performance
of a x4 link. This is caused by circumstances where the 80333 must discard a large portion of the
data it receives across the upstream link. Notably, anytime the 80333 services an incorrect prefetch,
or anytime the 80333 services interleaved requests from multi-function devices, the 80333 must
discard data.
Devices that rely heavily on prefetching, or multi-function devices that request data in an
interleaved fashion, are the most likely to experience degraded performance.
When possible, system designers must reduce the amount of prefetching allowed to devices behind
the 80333.
No
PCI Express* ESD enhancement requires a change to register setting
Validation has shown PCI Express* ESD enhancement, with changes to undisclosed registers in
the 80333.
The workaround below increases the margin for the eye and therefore results in a healthier,
improved PCI Express* link.
BIOS or firmware must set F0/F2:R260h bit[15] to 1 and clear F0/F2:R270h bit[31] to 0. This
workaround is required for both cold and warm reset.
No
steppings. See the
SKP ordered set might not be sent within required interval during link
recovery when a packet is pending
During Link Recovery on the PCI Express* port, the 80333 might fail to transmit a SKP ordered
set within the required time interval as defined in the PCI Express* Specification, Revision 1.0a
when a TLP or DLLP was pending when the link entered Recovery.Idle state.
When the receiving device depends upon receipt of an SKP ordered set to progress through Link
Recovery, a time-out occurs, resulting in Link Down and automatic reinitialization of the
PCI Express* link. A link transitions through recovery only under exceptional operational
conditions. Following the Link Recovery time-out and reinitialization, the PCI Express* link can
be expected to resume normal operation unless the original Link Recovery condition was entered
as a result of a hard failure mechanism.
None
No
Fix. Not to be fixed. See the
Fix. Not to be fixed. See the
Fix. Not to be fixed. The BIOS/firmware workaround must be left in place for all 80333
Table , “Summary Table of Changes” on page
Table , “Summary Table of Changes” on page
Table , “Summary Table of Changes” on page
7.
Specification Update
7.
7.