QG80333M500 S L9BH Intel, QG80333M500 S L9BH Datasheet - Page 32

• Manufacturer Part Number: QG80333M500 S L9BH
• Manufacturer: Intel

Specifications of QG80333M500 S L9BH

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Intel® 80333 I/O Processor
Specification Changes
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if MemoryType is DDR-II
Write 0x2 to DCALADDR (Setting BA[1:0] for EMRS(2))
Write 0x81000003 to DCALCSR (issue EMRS command to CS0)
Wait for DCALCSR[31] to report ‘Operation Completed’
Write 0x81100003 to DCALCSR (issue EMRS command to CS1)
Wait for DCALCSR[31] to report ‘Operation Completed’
Write 0x3 to DCALADDR (Setting BA[1:0] for EMRS(3))
Write 0x81000003 to DCALCSR (issue EMRS command to CS0)
Wait for DCALCSR[31] to report ‘Operation Completed’
Write 0x81100003 to DCALCSR (issue EMRS command to CS1)
Wait for DCALCSR[31] to report ‘Operation Completed’
endif
REFCLK relationship to voltage rails
The current 80333 design guide (305434) states the following in section 10.1:
"Also, all 80333 voltage rails must be stable and within their operating ranges before the PCI
Express differential clocks REFCLK+ and REFCLK- begin running. This is a requirement for all
devices with PCI Express interfaces."
When the 80333 is on an add-in card, only 3.3V and 12V are provided to the slot, therefore, a local
regulator is required for 1.5V and 2.5V generation. Due to the delay by the local regulators,
REFCLK may already be provided before the power rails are stable. If this is the case, no device
overstress will occur, provided that the REFCLK input current does not exceed 900mA and the
input voltage does not exceed the PCI Express specification of 1.15V. REFCLK buffers on many
Intel platforms show an input current of 15.6mA, well under the 900mA limit.
The requirement for "all 80333 voltage rails to be stable before the PCI Express differential clocks
REFCLK+ and REFCLK- begin running" is no longer a requirement.
Case temperature (Tcase) change
To be consistent with the production test environment, the case temperature (Tcase) for the 80333
I/O processor has been changed from 105
PWRGD and RSTIN# sequencing
Strapping RSTIN# high (as stated in the 80333 design guide v001, table 3), bringing RSTIN# up
prior to PWRGD rising edge or tying PWRGD and RSTIN# together, could result in platform
failures.
The correct sequencing between PWRGD and RSTIN#, is for the rising edge of RSTIN# to follow
the rising edge of PWRGD by at least 1ms.
Internal Clock Misalignment
Due to non-core
Intel is screening parts to eliminate the probability of occurrence. Until this is fixed in a future
stepping, a screen has been implemented which will screen out parts exhibiting this issue with a
VCC15 greater than 1.46v.
With the screen at 1.46v, the on-board 1.5v power rail should not be allowed to go below 1.46v, as
this would increase the risk of failure. The 1.5v rail minimum is currently specified in the datasheet
as 1.425v, therefore for screened parts, the minimum is changed to 1.46v.
Fixed. This issue was fixed in the A-1 stepping of the product.
Erratum 35, Internal Clock Misalignment Can Cause Processor Hang, on page
o
c to 95
o
c.
Specification Update
26,