QG80333M500 S L9BH Intel, QG80333M500 S L9BH Datasheet - Page 45

• Manufacturer Part Number: QG80333M500 S L9BH
• Manufacturer: Intel

Specifications of QG80333M500 S L9BH

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

43.
Issue:
Status:
44.
Issue:
Status:
45.
Issue:
Status:
46.
Issue:
47.
Issue:
Status:
Specification Update
RCVDLY setting for DDR-I memory
The Receive Enable Delay Register (RCVDLY at FFFF_F550h) is used for DQS receive enable
calibration. In other words, RCVDLY adjusts the memory controllers relationship of DQS to an
internal M_CLK.
The RCVDLY value is highly dependant on the board layout and DIMM characteristics. Also, the
memory controller only supports a non integer CAS latency (tCAS = 2.5, SDCR0.9:8) for DDR-I,
which means that RCVDLY may need to be adjusted because DQS is no longer synchronized with
M_CLK.
Therefore, when using DDR-I memory the RCVDLY default setting of 5, may need to be changed
to 6 or 7 to operate correctly with a specific DIMM based on the board layout. For example, the
Redboot reference code provided by Intel uses a value to 7 in order to allow for a wider
compatibility with various DIMMs.
No
Embedded Usage Models
The 80333 I/O Processor was designed to be used as a PCI-Express endpoint. The PCI-Express
interface on the 80333 does not have root complex support, therefore it cannot be used in an
embedded application unless there is an upstream root complex that can control the 80333
PCI-Express port.
Also, data transfers between the A-segment PCI bus and B-segment PCI bus is not a supported
configuration.
interface.
No
ATUBAR3 Functionality
The private memory window of the PCI A-segment defines an address range that the 80333 uses to
map private devices to, and to locate local memory for private device access. This range is
intended to be mapped to the ATUs private BAR window (ATUBAR3) and the private device
BARs. Note that even when the private addressing is enabled, the normal 80333 behavior defined
for BME, MSE, IOSE bits in the ATUCMD register are still true. Therefore, when the ATU
Memory Space Enable bit is cleared, all ATU BARs including ATUBAR3 will be unable to claim
any memory transactions. For example, this bit is typically cleared during a PCI bus scan /
enumeration.
No
VREF isolation for Battery Back-up (BBU) mode
During battery back-up (BBU) mode, the DIMM power can be isolated from the 80333 IOP power.
This isolation should also include the VREF signal for the DIMM interface. Due to leakage, the
VREF signal for the DIMM should be isolated from the VREF signal for the IOP. This is to ensure
that VREF for the DIMM is not disturbed as the IOP powers down when entering battery back-up
(BBU) mode. The isolation can be provided by using separate voltage dividers or a FET.
For related issues, refer to Specification Clarification 27,
Back-Up (BBU) mode” on page
I2C Unit Enabling
Software must guarantee that the I2C bus is idle before enabling the I2C unit. Failure to do so could
result in unstable behavior. The IBMR register can be used to monitor the state of the SCL and
SDA pins in order to determine bus activity. The I2C Bus Busy bit in the I2C Status Register
(ISR.3) can not be used for this purpose, as it is only valid when the I2C unit is enabled.
No
Fix. See the
Fix. See the
Fix. See the
Fix. See the
Table , “Summary Table of Changes” on page
Table , “Summary Table of Changes” on page
Table , “Summary Table of Changes” on page
Table , “Summary Table of Changes” on page 7
These two PCI busses are independent and only bridge to the PCI-Express
41.
“Power plane isolation for Battery
7.
7.
7.
Specification Clarifications
Intel® 80333 I/O Processor
45