QG80333M500 S L9BH Intel, QG80333M500 S L9BH Datasheet - Page 8

• Manufacturer Part Number: QG80333M500 S L9BH
• Manufacturer: Intel

Specifications of QG80333M500 S L9BH

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Intel® 80333 I/O Processor
Summary Table of Changes
Non-Core Errata (Sheet 1 of 2)
8
No.
10
12
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23
24
25
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11
1
2
3
4
5
6
7
8
9
A-0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Stepping
A-1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
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X
Page
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Status
No Fix
No Fix
No Fix
No Fix
No Fix
No Fix
No Fix
No Fix
No Fix
No Fix
No Fix
No Fix
No Fix
No Fix
No Fix
No Fix
No Fix
No Fix
No Fix
No Fix
No Fix
No Fix
No Fix
No Fix
No Fix
No Fix
No Fix
No Fix
No Fix
No Fix
CAS latency of three not supported for DDR-II On-Die Termination (ODT)
Legacy power fail mechanism does not work
A_REQ64# and B_REQ64# initialization pattern timing violation in PCI-33 mode
Secondary Bus Number register (PEBSBBNR) provides incorrect bus number
Boundary scan multi-chip module implementation
PCI Express* traffic class (TC) bit[2] ignored for malformed packet checks
Auto-Refresh command also generates a Precharge All command on DDR bus
Coalesced writes to 32-bit memory can cause data corruption
ATU passing rules operation in PCI mode
Secondary bus PCI RST# pulse prior to the rising edge of PWRGD
VPD Data Register bit[19] is not read/write
PCI Express* Correctable Error Mask Bits
DMA CRC result is byte-reversed
CRC corruption on PCI-to-local DMA transfers
IOAPIC End of Interrupt (EOI) Register is Read-Write, should be Write-Only
Unreliable PCI Express* link operation when L0s active state power management
is enabled
SSE bit set for PERR# assertion when error reporting is masked
Data Parity Error detected on PCI/X interface fails to propagate bad parity
ATU claims PCI commands 8 and 9 when issued as Dual Address Cycle (DAC)
Failure to train down in presence of degraded lane
PCI Express* and PCI-X header logs and first-error pointers do not remain sticky
through reset
Incorrect default value for PCI Express* Flow Control Protocol Error Severity bit
Power State bits in PCI Express* Power Management Status and Control Register
mistakenly accept reserved values
Performance across an upstream ×1 PCI Express* link is less than expected
PCI Express* ESD enhancement requires a change to register setting
SKP ordered set might not be sent within required interval during link recovery
when a packet is pending
SERR fatal/non-fatal error message enabled with incorrect error message
enabled bit
Configuration write to offset 70h of A- and B-bridge (PM_CSR - PCI Express
Power Management Control/Status Register) using non-continous byte enables
does not capture the data value
The 80333 might become unresponsive when transitioning into the D3 power
state
Bus Interface Unit (BIU) claims DAC addresses in the range of the Memory
Mapped Registers (MMR)
Errata
Specification Update