QG80333M500 S L9BH Intel, QG80333M500 S L9BH Datasheet - Page 33

• Manufacturer Part Number: QG80333M500 S L9BH
• Manufacturer: Intel

Specifications of QG80333M500 S L9BH

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Specification Clarifications
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Specification Update
PCI Express* to PCI-X Bridge does not support Device ID Messaging (DIM)
The PCI Express* to PCI-X Bridge does not forward DIM transactions. This is an optional feature
in the PCI Express* to PCI/PCI-X Bridge Specification, Rev. 1.0.
No
64 MB and 2 GB DDR333 capacities not tested in post-silicon validation
Intel is not able to test 64 MB and 2 GB DDR333 DIMMs due to availability. Intel cannot
guarantee proper functionality since validation cannot be completed.
No
DDR-II 400 unbuffered DIMMs are not supported
The 80333 supports DDR333 buffered (registered) and unbuffered DIMMs, but supports only
DDR-II 400 buffered (registered) DIMMs. DDR-II 400 unbuffered DIMMs are not supported.
No
Memory map for 2 GByte of DDR memory
The 80333 can support up to 2 Gbytes of DDR SDRAM, but it cannot cross a 2 GB boundary.
Therefore it must be mapped to either 0x00000000–0x7FFFFFFF or 0x80000000–0XFFFFFFFF.
Either range conflicts with one or more of the statically assigned regions. The recommendation is
to disable the direct outbound ATU window, in order to use the larger 2 GB memory, by clearing
ATUCR[8] (default setting is 0–disabled).
No
PCI configuration write anomaly when clearing BINIT[1]
There is an anomaly when the ATU does a configuration write to BINIT[1] of the A-segment
configuration header. When clearing bit[1] by writing 00000009h to the BINIT Configuration
Register (offset FCh), the PCI bridge retries the write the first time. The PCI specification states
that no data is to be transferred on retries. The configuration register is updated to 00000009h;
therefore, data did get transferred on the retry. The PCI bridge ignores the second write, giving a
master abort. BINIT[1] has a bit attribute of Read and Write Once (RWOS).
The worst-case implication is that a master abort error occurs when turning off inbound
configuration accesses (BINIT[1]–A-segment).
This anomaly is not seen when the A-segment is running in PCI-X mode, but only when in PCI
mode.
No
PWRGD and PERST# are the same signals
The 80333 uses PWRGD to identify the primary reset signal as described in the PCI Express Card
Electromechanical Specification, Revision 1.0. This is the same signal as PERST#, which is
described in the PCI Express Card Electromechanical Specification, Revision 1.0a.
No
Fix. See the
Fix. See the
Fix. See the
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Fix. See the
Fix. See the
Table , “Summary Table of Changes” on page
Table , “Summary Table of Changes” on page
Table , “Summary Table of Changes” on page
Table , “Summary Table of Changes” on page
Table , “Summary Table of Changes” on page
Table , “Summary Table of Changes” on page
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Specification Clarifications
Intel® 80333 I/O Processor
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