QG80333M500 S L9BH Intel, QG80333M500 S L9BH Datasheet - Page 44

• Manufacturer Part Number: QG80333M500 S L9BH
• Manufacturer: Intel

Specifications of QG80333M500 S L9BH

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Intel® 80333 I/O Processor
Specification Clarifications
40.
Issue:
Status:
41.
Issue:
Status:
42.
Issue:
Status:
44
Multi-Transaction Timer grants fewer clocks in PCI mode than expected
The Multi-Transaction Timer (MTT, offset 42), in the bridge configuration header of the 80333,
specifies the number of clocks that GNT# asserts to a master device on the PCI bus. When running
in PCI-X mode, the number of clocks granted matches the value programmed in the MTT, but
when in PCI mode, the master is granted 16 clocks fewer than the value programmed in the MTT.
The number of GNT# cycles is measured from the assertion of FRAME# to the deassertion of
GNT# with REQ# asserted during the whole time. This behavior occurs on both the A- and B-bus
segments and at both PCI frequencies (33 MHz and 66 MHz). For example, when the MTT value is
0x18, it produces 0x8 clocks between the assertion of FRAME# and deassertion of GNT#. Another
example: when the MTT value is 0x30, it produces 0x20 clocks between the assertion of FRAME#
and deassertion of GNT#.
No
Byte Enables (BE) not included in PCI delayed reads can cause data
corruption
A PCI device on one of the secondary busses that generates a zero-length read request can cause
data corruption in platforms utilizing non-Intel® MCH components, as the byte enables (BE) are
not included by the 80333 bridge in matching completions to PCI delayed read requests. All Intel®
MCH devices return data consistent with the address of a zero-length read request. Thus, no
corruption can occur when a subsequent non-zero-length read is inadvertently completed with data
returned on behalf of the zero-length request, but this behavior is not required by specification.
The following is an example case:
1. A memory read request with zero BE is issued over PCI; a corresponding zero-length read
results on PCI Express* to the host.
2. A PCI device on the same PCI segment issues a MR/MRL/MRM to the same address with valid
BEs.
3. The 80333 bridge matches the completion for the Memory Read request on line 1 to the request
on line 2 (in other words, BEs are ignored).
4. Unspecified data (returned for the zero-length read request) is driven to the PCI card, resulting in
data corruption.
Note: This affects PCI mode exclusively, and is not an issue when the secondary busses are
operating in PCI-X mode. Whether corruption can occur through this mechanism is dependent
upon the behavior of the non-Intel® MCH component. If the MCH in use behaves similarly to
Intel® MCH designs, there is no exposure to data corruption, and the incomplete completion match
does not have any side effects.
No
Interleaving AAU descriptors
The P+Q capability is enabled in the AAU globally (ACR.3), not on a descriptor by descriptor
basis. Therefore if enabled, all descriptors are processed as P+Q descriptor formats. If disabled, all
descriptors are processed as prior AAU definitions (ie - straight XOR). In order to mix RAID-5
with P+Q RAID-6, enable P+Q RAID-6 GF Multiply for the AAU, and build all RAID-5 XOR
descriptors as P+Q RAID-6 descriptors, where the GF Multiplier Byte values are all 0x01.
No
Fix. See the
Fix. See the
Fix. See the
Table , “Summary Table of Changes” on page
Table , “Summary Table of Changes” on page
Table , “Summary Table of Changes” on page
7.
7.
7.
Specification Update