QG80333M500 S L9BH Intel, QG80333M500 S L9BH Datasheet - Page 36

• Manufacturer Part Number: QG80333M500 S L9BH
• Manufacturer: Intel

Specifications of QG80333M500 S L9BH

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Intel® 80333 I/O Processor
Specification Clarifications
14.
Issue:
Status:
15.
Issue:
Status:
16.
Issue:
Status:
36
Potential race condition with Interrupt Controller Unit status bits
There is a slight lag in the time it takes between clearing a status bit inside the unit and the
corresponding bit in the Interrupt Controller Unit Status Register getting cleared. This has the
potential of generating a false interrupt, meaning that the Intel XScale
but the handler is not able to find any source reported in the ICU registers. This condition can be
avoided by adding a read from any ICU register, after the bit is cleared in the local unit before
returning from the interrupt handler. The data from this read can be ignored, but the read itself
creates enough latency to allow the updated status to propagate to the ICU.
No
Reset Internal Bus (PCSR[5]) usage
PCI bus data corruption can occur when the reset internal bus bit is not used correctly. PCSR[5] can
be used to reset the internal bus. This resets all memory-mapped registers and the ATU
configuration header space. This bit is read/write-capable from both the internal bus and PCI bus.
For both PCI and PCI-X modes, make sure the following steps occur when setting PCSR[5]:
No
PCI Express* Transaction Header Log register repeats on offset 124 and 128
The lower 32 bits of the address of the Single Address Cycle (SAC) are mirrored onto the upper
32 bits in the log register giving the appearance that a Dual Address Cycle (DAC, 64-bit address
transaction) occurred instead of a SAC (Single Address Cycle, 32-bit address transaction).
The lower 32 bits of the address are on the third DWord and the upper are on the fourth DWord.
The fourth DWord is “reserved” for a SAC transaction. So, instead of the fourth DWord defaulting
to 0 as expected, it actually mirrors the third DWord.
For example: For a 32-bit TLP (memory write with poisoned bit set) downstream transaction to the
80333, the header log (offset 11C–12B) could look like this:
No
1. Clear Bus Master (ATUCMD[2]) Enable and Memory Enable (ATUCMD[1]).
2. Wait for both the outbound (PCSR[15]) and inbound (PCSR[14]) read transaction queue busy
3. Make sure no PCI configuration read/write cycles targeting the ATU are in progress, except
4. Set the Reset Internal Bus bit.
5. Wait for 40 PCI clocks.
Fix. See the
Fix. See the
Fix. See the
bits to clear.
the reset configuration write, when applicable.
Offset: 0x11C, Before: 0x00000000, After: 0x40004005
Offset: 0x120, Before: 0x00000000, After: 0x000000FF
Offset: 0x124, Before: 0x00000000, After: 0x06000000
Offset: 0x128, Before: 0x00000000, After: 0x06000000
Table , “Summary Table of Changes” on page
Table , “Summary Table of Changes” on page
Table , “Summary Table of Changes” on page
7.
7.
7.
®
processor is interrupted,
Specification Update