QG80333M500 S L9BH Intel, QG80333M500 S L9BH Datasheet - Page 28

• Manufacturer Part Number: QG80333M500 S L9BH
• Manufacturer: Intel

Specifications of QG80333M500 S L9BH

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Intel® 80333 I/O Processor
Core Errata
3.
Workaround:
Status:
4.
Problem:
Workaround:
Status:
28
Performance Monitor Unit event 0x1 can be incremented erroneously by
unrelated events
Event 0x1 in the Performance Monitor Unit (PMU) can be used to count cycles in which the
instruction cache cannot deliver an instruction. The only cycles counted are supposed to be those
due to an instruction cache miss or an instruction TLB miss. The following unrelated events in the
core, also causes the corresponding count to increment when event number 0x1 is being monitored:
Each of the preceding items can cause the performance-monitoring count to increment several
times. The resulting performance monitoring count can be higher than expected when the
preceding items occur, but has not been observed to be lower than expected.
There is no way to obtain the correct number of cycles stalled due to instruction cache misses and
instruction TLB misses. Extra counts, due to branch instructions mispredicted by the BTB, might
be one component of the unwanted count that can be filtered out.
The number of mispredicted branches also can be monitored using performance-monitoring event
0x6 during the same time period as event 0x1. The mispredicted branch number can then be
subtracted from the instruction cache stall number generated by the performance monitor to get a
value closer to the correct one. This workaround addresses only counts contributed by branches
that the BTB is able to predict.
All the items in the preceding bulleted list still affect the count. Depending on the nature of the
code being monitored, this workaround might have limited value.
No
In Special Debug State, back-to-back memory operations—in which the first
instruction aborts—can cause a hang
When back-to-back memory operations occur in the Special Debug State (SDS, used by ICE and
Debug vendors), and the first memory operation gets a precise data abort, the first memory
operation is correctly cancelled and no abort occurs. Depending on the timing, however, the second
memory operation might not work correctly. The data cache might internally cancel the second
operation, but the register file may have scoreboarded registers for that second memory operation.
The effect is that the core might hang (due to a permanently scoreboarded register) or that a store
operation might be incorrectly cancelled.
In Special Debug State, any memory operation that can cause a precise data abort must be followed
by a write-buffer drain operation. This precludes further memory operations from being in the pipe
when the abort occurs. Load Multiple/Store Multiple that might cause precise data aborts must not
be used.
No
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Fix. See the
Fix. See the
Any architectural event (for example, IRQ, data abort)
MSR instructions which alter the CPSR control bits
Some branch instructions, including indirect branches and those mispredicted by the BTB
CP15 MCR instructions to registers 7, 8, 9, or 10, which involve the instruction cache or the
instruction TLB.
Table , “Summary Table of Changes” on page
Table , “Summary Table of Changes” on page
7.
7.
Specification Update