SSTE32882KA1AKG IDT, Integrated Device Technology Inc, SSTE32882KA1AKG Datasheet - Page 18

• Manufacturer Part Number: SSTE32882KA1AKG
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of SSTE32882KA1AKG

• Lead Free Status / RoHS Status: Compliant

1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
V
SSTE32882KA1
1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
Symbol
OX
1 DCKE0/1, DODT0/1, DA0..DA15, DBA0..DBA2, DRAS, DCAS, DWE, PAR_IN, DCS[1:0] when QCSEN = HIGH, DCS[3:0] when QCSEN = LOW.
2 RESET, MIRROR
3 This spec applies only when both CK and CK are actively driven LOW. It does not apply when CK/CK are floating.
4 Extended range for Vix is only allowed for clock (CK and CK) and if single-ended clock input signals CK and CK are monotonic with a single-ended swing VSEL / VSEH
of at least VDD/2 +/-275 mV, and when the differential slew rate of CK - CK is larger than 4 V/ns.
5 Extended range for Vix is only allowed for clock (CK and CK) and if single-ended clock input signals CK and CK are monotonic with a single-ended swing VSEL / VSEH
of at least VDD/2 +/-243 mV, and when the differential slew rate of CK - CK is larger than 4 V/ns.
6 Extended range for Vix is only allowed for clock (CK and CK) and if single-ended clock input signals CK and CK are monotonic with a single-ended swing VSEL / VSEH
of at least VDD/2 +/-243 mV, and when the differential slew rate of CK - CK is larger than 3.6 V/ns
7 VID is the magnitude of the difference between the input level on CK and the input level on CK See Diagram (Voltage waveforms; input clock)
8 Default settings
Differential Output Crosspoint Voltage (1.5V Operation)
Differential Output Crosspoint Voltage (1.35V Operation)
THE INFORMATION IN THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE
Parameter
Yn, Yn
Yn, Yn
Signals
18
0.5xV
0.5xV
DD
DD
Min
– 100 mV
– 90 mV
COMMERCIAL TEMPERATURE RANGE
SSTE32882KA1
Nom
–
–
0.5xV
0.5xV
DD
DD
Max
+ 100 mV
+ 90 mV
Unit
7314/8
V
V