SSTE32882KA1AKG IDT, Integrated Device Technology Inc, SSTE32882KA1AKG Datasheet - Page 34

• Manufacturer Part Number: SSTE32882KA1AKG
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of SSTE32882KA1AKG

• Lead Free Status / RoHS Status: Compliant

1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
SSTE32882KA1
1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
4. This skew represents the absolute Qn skew compared to the output clock (Yn), and contains the register pad skew, clock skew and package
routing skew (See “Qn Output Skew for Standard 3/4-Clock Pre-Launch”). The output clock jitter is not included in this skew. The Qn
output can either be early or late. This parameter applies to each side of the register independently. The parameter includes the skew related
to simultaneous switching noise (SSO).
5. This parameter measures the delay from the rising differential input clock which samples incoming C/A to the rising differential output
clock that will be used to sample the same C/A data. t
well as tracking error and jitter. Including this variation t
6. See “Measurement Requirement for t
7. Implies a -3 dB bandwidth and jitter peaking of 3 dB.
Y2
Y2
THE INFORMATION IN THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE
Y0
Y0
Y2
Y2
t
CK
STAOFF
and t
t
CKSK
DYNOFF
STAOFF
Clock Output (Yn) Skew
STAOFF
“.
may vary by the amount of t
may not exceed the limits set by t
t
CKSK
34
DYNOFF
STAOFF(MIN)
based on voltage and temperature drift as
COMMERCIAL TEMPERATURE RANGE
SSTE32882KA1
and t
STAOFF(MAX).
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