SSTE32882KA1AKG IDT, Integrated Device Technology Inc, SSTE32882KA1AKG Datasheet - Page 29

• Manufacturer Part Number: SSTE32882KA1AKG
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of SSTE32882KA1AKG

• Lead Free Status / RoHS Status: Compliant

AC Specifications - Output Timing Requirements
1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
SSTE32882KA1
1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
Symbol
t
t
PDM
t
1
2
3
DIS
EN
1 CK and Yn left out for better visibility.
2 RCA0 is re-driven command address signal based on input CA0.
C/A
pre-
launch
Standard
Input
See “Qn and Yn Load Circuit” diagram.
See “Propagation Delay Timing” diagram below.
See “Voltage Waveforms Address Floating” diagram.
Propagation delay, single-bit
switching (1.25V operation)
Output disable time (1/2-Clock
pre-launch)
Output enable time (1/2-Clock
pre-launch)
QxCKEx,
QxODTx
QxCKEx,
QxODTx
Qn(C/A)
Qn(C/A)
QxCSx,
QxCSx
Yn
Yn
CK
DCS
C/A
(1)
(1)
(1)
Parameter
THE INFORMATION IN THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE
t
1
PDM
CA0
n
CK/CK to output
Yn/Yn (falling
edge) to output
float
Yn/Yn (falling
edge) output
driving
RCA0
RCA0
Conditions
n+1
(2)
3
3/4 Clock Qn(C/A) pre-launch time
Propagation Delay Timing
n+2
2
tQSK1(max)
tQSK1(min)
DDR3U-800/ 1066
n+3
(DDR3U 1.25V)
Min
0.5+
0.65
0.5-
n+4
29
Max
1.35
n+5
DDR3U -1333/1600
tQSK1(max)
tQSK1(min)
COMMERCIAL TEMPERATURE RANGE
Min
SSTE32882KA1
0.5+
0.65
0.5-
n+6
Max
1.35
Unit
ns
ps
ps
7314/8