SSTE32882KA1AKG IDT, Integrated Device Technology Inc, SSTE32882KA1AKG Datasheet - Page 32

• Manufacturer Part Number: SSTE32882KA1AKG
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of SSTE32882KA1AKG

• Lead Free Status / RoHS Status: Compliant

1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
t
t
BAND
SSTE32882KA1
1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
DYNOFF
Symbol
1. This skew represents the absolute output clock skew and contains the pad skew and package skew (See “Clock Output (Yn) Skew”). This
parameter is specified for the clock pairs on each side of the register independently. The skew is applicable to left side clock pairs between
Y0/Y0 and Y2/Y2, as well as right side of the clock pairs between Y1/Y1 and Y3/Y3. This is not a tested parameter and has to be considered
as a design goal only.
2. This skew represents the absolute Qn skew compared to the output clock (Yn), and contains the register pad skew, clock skew and package
routing skew (See “Qn Output Skew for Standard 1/2-Clock Pre-Launch”). The output clock jitter is not included in this skew. The Qn
output can either be early or late. This parameter applies to each side of the register independently. The parameter includes the skew related
to simultaneous switching noise (SSO).
3. The parameter is a measure of the output clock pulse width HIGH/LOW. The output clock duty cycle can be calculated based on t
4. This skew represents the absolute Qn skew compared to the output clock (Yn), and contains the register pad skew, clock skew and package
routing skew (See “Qn Output Skew for Standard 3/4-Clock Pre-Launch”). The output clock jitter is not included in this skew. The Qn
output can either be early or late. This parameter applies to each side of the register independently. The parameter includes the skew related
to simultaneous switching noise (SSO).
5. This parameter measures the delay from the rising differential input clock which samples incoming C/A to the rising differential output
clock that will be used to sample the same C/A data. t
well as tracking error and jitter. Including this variation t
6. See “Measurement Requirement for t
7. Implies a -3 dB bandwidth and jitter peaking of 3 dB.
6
Maximum variation in
delay between the input
& output clock
SSC modulation
frequency
SSC clock input
frequency deviation
PLL Loop bandwidth
(-3 dB from unity gain)
Parameter
THE INFORMATION IN THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE
Conditions
STAOFF
and t
0.00
25
DDR3-800
30
-
DDR3/
DYNOFF
7
STAOFF
STAOFF
-0.5
160
33
“.
may vary by the amount of t
may not exceed the limits set by t
DDR3L-1066
0.00
30
30
-
DDR3/
7
-0.5
130
33
DDR3L-1333
0.00
35
30
32
-
DDR3/
7
DYNOFF
110
-0.5
33
STAOFF(MIN)
based on voltage and temperature drift as
DDR3L-1600
0.00
40
COMMERCIAL TEMPERATURE RANGE
30
-
DDR3/
7
SSTE32882KA1
-0.5
90
33
-
and t
STAOFF(MAX).
0.00
DDR3-1866
45
30
-
7
-0.5
70
33
-
PW
MHz
7314/8
Unit
kHz
ps
%
.