SSTE32882KA1AKG IDT, Integrated Device Technology Inc, SSTE32882KA1AKG Datasheet - Page 36

• Manufacturer Part Number: SSTE32882KA1AKG
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of SSTE32882KA1AKG

• Lead Free Status / RoHS Status: Compliant

Clock Driver Characteristics at Test Frequency (frequency band 2)
1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
SSTE32882KA1
1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
t
t
t
Symbol
QSK
QSK
t
JIT
t
t
JIT
DYNOFF
1
2
Skew”). This parameter is specified for the clock pairs on each side of the register independently. The skew is applicable to the
left side of the clock pair between Y0/Y0 and Y2/Y2, as well as the right side of the clock pair between Y1/Y1 and Y3/Y3.
3
and package routing skew (see “Qn Output Skew for Standard 1/2 Clock Pre-Launch”). The output clock jitter is not included in
this skew. This parameter applies to each side of the register independently. The Qn output can either be early or late.
4
and package routing skew. The output clock jitter is not included in this skew. This parameter applies to each side of the register
independently. This parameter includes the skew related to Simultaneous Switching Noise (SSO). The Qn output can either be
early or late.
5
and package routing skew (see “Qn Output Skew for Standard 3/4 Clock Pre-Launch”). The output clock jitter is not included in
this skew. This parameter applies to each side of the register independently. The Qn output can either be early or late.
6
and package routing skew. The output clock jitter is not included in this skew. This parameter applies to each side of the register
independently. This parameter includes the skew related to Simultaneous Switching Noise (SSO). The Qn output can either be
early or late.
7 The re-driven clock signal is ideally centered in the address/control signal eye. This parameter describes the dynamic deviation
from this ideal position including jitter and dynamic phase offset.
t
t
JIT
t
t
QSK
QSK
CKSK
STAB
(
(
HPER
1
2
(
PER
CC
SSO 4
SSO 6
1
2
This skew represents the absolute output clock skew and contains the pad skew and package skew.
This skew represents the absolute output clock skew and contains the pad skew and package skew (see “Clock Output (Yn)
This skew represents the absolute Qn skew compared to the output clock Yn, and contains the register pad skew, clock skew,
This skew represents the absolute Qn skew compared to the output clock Yn, and contains the register pad skew, clock skew,
This skew represents the absolute Qn skew compared to the output clock Yn, and contains the register pad skew, clock skew,
This skew represents the absolute Qn skew compared to the output clock Yn, and contains the register pad skew, clock skew,
3
5
)
)
)
THE INFORMATION IN THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE
Cycle-to-cycle period jitter
Stabilization time
Total Clock Output skew
Fractional Clock Output skew
Yn Clock Period jitter
Half period jitter
Qn Output to clock tolerance (Standard
1/2-Clock Pre-Launch)
Output clock tolerance (3/4 Clock Pre-Launch)
Maximum re-driven dynamic clock offset
Parameter
1
2
7
Output Inversion
Enabled
Output Inversion
Disabled
Output Inversion
Enabled
Output Inversion
Disabled
Conditions
36
Min.
-160
-200
-100
-100
-100
-100
-500
0
−
COMMERCIAL TEMPERATURE RANGE
SSTE32882KA1
Max.
TBD
TBD
TBD
TBD
TBD
160
100
160
200
500
15
Unit
ps
us
ps
ps
ps
ps
ps
ps
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