PEB20571FV31XP Infineon Technologies, PEB20571FV31XP Datasheet - Page 266

• Manufacturer Part Number: PEB20571FV31XP
• Manufacturer: Infineon Technologies

Specifications of PEB20571FV31XP

• Lead Free Status / Rohs Status: Compliant

8.6
8.6.1
The exact behavior required from every P interface signal during a DMA access,
determined according to the following modes:
1. Motorola/Intel Mode: Determined by the MODE input pin.
2. Normal/Fly-By mode: Programmable mode, in the control register of the P-interface.
In any mode, the DACK input alone is used to indicate that this is a DMA transaction,
and to select the DMA mail-box. An activation of CS is not required in such cases.
8.6.1.1
In this mode DS is used for timing the access, while R/W is used to distinguish between
DMA read transactions and DMA write transactions. The R/W input signal is used
differently in Normal mode and in Fly-By mode. The next table details the way in which
R/W should be used in each mode, during DMA transactions:
Table 63
Mode
Normal (Non-Fly-By)
Fly-By
In Fly-By mode R/W is used inverted, because the same signal, R/W, is required for
concurrent accessing of an external memory device.
Data Sheet
AC Characteristics
DMA Access Timing
DMA Access Timing In Motorola Mode
R/W Behavior During DMA Transactions in Normal and in Fly-By
Mode
R/W = ‘0’
Write DMA transaction.
(A response to DMA
transmitter request)
Read DMA transaction.
(A response to DMA
receiver request)
Electrical Characteristics and Timing Diagrams
249
R/W = ‘1’
Read DMA transaction.
(A response to DMA receiver
request)
Write DMA transaction.
(A response to DMA transmitter
request)
PEB 20570
PEB 20571
2003-07-31