PEB20571FV31XP Infineon Technologies, PEB20571FV31XP Datasheet - Page 35

• Manufacturer Part Number: PEB20571FV31XP
• Manufacturer: Infineon Technologies

Specifications of PEB20571FV31XP

• Lead Free Status / Rohs Status: Compliant

Table 5
Pin
No.
87
88
76
78
77
74
82
Data Sheet
Symbol In (I)
PFS
PDC
RxD0 /
LRxD2
TxD0 /
LTxD2
TSC0 /
LRTS2
RxD2 /
LCTS2
TxD2 /
LCLK2
PCM Interface Ports 0 ... 3 / LNC Ports 2 ... 3 (DELIC-LC)
Out (O)
I/O
I/O
I
I
O
O(OD)
O
O
I
I
O
I/O
During
Reset
I
I
I
High
Z
Reset
Counter
Bypass”
strap
pull-up
refer to
Page 38
I
weak
low
After
Reset
I
I
I
High
Z
H
I
weak
low
18
Function
PCM Frame Synchronization Clock.
8 kHz/4 kHz when input or 8 kHz when
output.
Note: When PFS is configured as 4 kHz
PCM Data Clock (input or output)
2.048 MHz, 4.096 MHz,
8.192 MHz, 16.384 MHz
PCM Receive Data Port 0
LNC Receive Serial Data Port 2
(Async mode)
PCM Transmit Data Port 0
LNC Transmit Serial Data Port 2
Async mode)
PCM Tristate Control Port 0
Supplies a control signal for an external
driver (’low’ when the corresponding TxD-
output is valid).
LNC2 Request To Send
’request-to-send’ functionality
(Async mode)
PCM Receive Data Port 2
LNC2 ’clear-to-send’ functionality
(Async mode)
PCM Transmit Data Port 2
LNC External Clock Port 2
When configured as output may be driven
at the following frequencies:
2.048 MHz, 4.096 MHz,
8.192 MHz, 16.384 MHz
input,
restricted to 2.048 MHz input.
PDC
configuration
Pin Description
PEB 20570
PEB 20571
2003-07-31
is