PEB20571FV31XT Infineon Technologies, PEB20571FV31XT Datasheet - Page 110

• Manufacturer Part Number: PEB20571FV31XT
• Manufacturer: Infineon Technologies

Specifications of PEB20571FV31XT

• Lead Free Status / Rohs Status: Compliant

4.2.10.4 DC-Balancing Bit (L-Bit)
In transmit (downstream) direction the L-bit is generated in compliance with ITU-T I.430:
• A balance bit is ‘0’ if the number of 0’s following the previous balance bit is odd.
• A balance bit is ‘1’ if the number of 0’s following the previous balance bit is even.
It is inserted by the VIP according to the Balancing Bit Control (BBC) bit sent to the VIP
by the DELIC via the CMD line.
In receive (upstream) direction, the DC balancing bit is received on the line, but not
evaluated.
4.2.11
Data processing and frame handling in the TRANSIU is fully DSP controlled. Serial data
received and transmitted on the TRANSIU Interface is arranged in the Shift Receive
RAM and Shift Transmit RAM.
The DSP processed bytes are stored in the TRANSIU Current Buffer. Every 8 kHz frame
the TRANSIU and DSP Current Buffers are switched.
4.2.11.1 S/T Mode Data Format
Data is received/transmitted at a nominal rate of 192 kbit/s. Each S/T data bit is
translated into two bits on IOM-2000: data (bit0) and control (bit1).
LT-S Mode Transmit Data Format
LT-S Mode Receive Data Format
Data Sheet
7
7
D-channel
D-channel
IOM-2000 Data Interface
6
6
Operation Mode Command/Status bits
Operation Mode Command/Status bits
F
5
5
x
a
B1 - channel data
B2 - channel data
B1-channel data
B2-channel data
F
4
4
x
a
93
M
3
3
x
S
2
2
x
Functional Description
1
x
1
x
PEB 20570
PEB 20571
2003-07-31
0
0
x
x