PEB20571FV31XT Infineon Technologies, PEB20571FV31XT Datasheet - Page 165

• Manufacturer Part Number: PEB20571FV31XT
• Manufacturer: Infineon Technologies

Specifications of PEB20571FV31XT

• Lead Free Status / Rohs Status: Compliant

Table 47
Address
D000 - D01F
D020 - D03F
D040 - D05F
D060 - D07F
D080 - D09F
D0A0 - D0BF
D0C0 - D0DF
D100 - D17F
D180 - D1FF
D1A0 - DFFF
Note: (*) The OAK memory mapped registers address space is described in the
For connecting a HDLC channel to a subscriber, the receive and transmit time slot
address must be determined. Usually the HDLC channels perform signalling to a
terminal which can be accessed via IOM2 or IOM2000 interface. Either D-channel
handling (2 bit) or signalling via a B-channel (8 bit) can be selected. The following figures
show the memory organization and help to determine initialization addresses for the
HDLC software registers.
The TRANSIU receive and transmit buffers are accessed directly by the DSP: switching-
and HDLC-tasks. Accesses to the ’Operation Mode Command and Status Bits’ are
possible via addresses: 6003
Data Sheet
following table:
(**) Accessing these addresses may cause unpredictable results.
OAK Memory Mapped Registers Address Space
H
CPU+DMA mailbox registers
Description
DCU registers
A/m-law registers
IOMU registers
PCMU registers
Clocks registers
TRANSIU registers
HDLCU registers
GHDLC registers
not used
+ n * 4 with n = 0..23.
148
DELIC Memory Structure
PEB 20570
PEB 20571
2003-07-31