PEB20571FV31XT Infineon Technologies, PEB20571FV31XT Datasheet - Page 45

• Manufacturer Part Number: PEB20571FV31XT
• Manufacturer: Infineon Technologies

Specifications of PEB20571FV31XT

• Lead Free Status / Rohs Status: Compliant

Table 13
Pin
No.
25
24
23
22
21
18
17
16
38
35
33
32
31
30
34
11
10
Data Sheet
Symbol
D7
D6
D5
D4
D3
D2
D1
D0
A6
A5
A3
A2
A1
A0
A4
DACK/
DREQR O
DREQT O
Microprocessor Bus Interface Pins (DELIC-PB)
Out (O)
I/O
The direction of these pins
depends on the value of the
following pins:
CS, RD/DS, WR / R/W and
MODE
I
I
In (I)
During
Reset
I
I
CLOCK
MASTER
Strap (pull-
down),
refer to
Table 19
ATION
BOOT
Strap (pull-
down),
refer to
Table 19
EMUL-
After
Reset
I
I
L
L
28
Function
Data Bus
When operated in address/data
multiplex mode, this bus is used as a
multiplexed AD bus. The Address pins
are externally connected to the AD bus.
Address Bus (bits 6 ... 0 except bit 4)
When operated in address/data
multiplex mode, this bus is used as a
multiplexed AD bus. The Data pins are
externally connected to the AD bus.
Bit 4 of the address bus/ DMA
Acknowledge
In non-DMA mode DACK/A4 input pin
should be connected to A4 of the µP
address-bus.
In DMA mode A4 is internally
connected to ‘0’.
DMA Request for Receive Direction
May be configured to active high or
active low (the default is active high)
DMA Request for Transmit Direction
May be configured to active high or
active low (the default is active high)
Pin Description
PEB 20570
PEB 20571
2003-07-31