PEB20571FV31XT Infineon Technologies, PEB20571FV31XT Datasheet - Page 278

• Manufacturer Part Number: PEB20571FV31XT
• Manufacturer: Infineon Technologies

Specifications of PEB20571FV31XT

• Lead Free Status / Rohs Status: Compliant

two IACK pulses, and the interrupt vector is issued as a response to the second one. The
vector’s source the OAK mailbox vector register (OVEC). The value stored in this
register is determined by the OAK, by writing operation.
IREQ is not deactivated by the IACK pulses directly, but by P writing access to OBUSY.
Table 73
Parameter
1)
Figure 69
Figure 70
Data Sheet
D-bus valid after IACK falling edge
D-bus float after IACK rising edge
IACK pulse width
Interval between two IACK pulses
IREQ delay after WR or DS
IACK
D
IACK
D
Valid only for Intel/Infineon mode.
Interrupt Acknowledge Cycle Timing
Interrupt Acknowledge Cycle Timing in Motorola Mode
Interrupt Acknowledge Cycle Timing in Intel/Infineon Mode
t
WA
Electrical Characteristics and Timing Diagrams
t
Symbol
t
t
t
t
t
HA
DADV
DADT
WA
HA
DWI
261
t
DADV
Limit Values
min.
0
0
25
10
t
vector
WA
1)
t
DADV
vector
max.
31
19
28
t
t
DADT
DADT
Unit
ns
ns
ns
ns
ns
Notes
Output load
capacity of
50 pF
PEB 20570
PEB 20571
2003-07-31