PEF2054NV21XT Infineon Technologies, PEF2054NV21XT Datasheet - Page 105

• Manufacturer Part Number: PEF2054NV21XT
• Manufacturer: Infineon Technologies

Specifications of PEF2054NV21XT

• Lead Free Status / Rohs Status: Compliant

PEB 2055
PEF 2055
Application Hints
Important Note
It should be noticed that there are some restrictions concerning the PCM to CFI data rate
ratio. If the CFI data rate is chosen higher than the PCM data rate, no restrictions apply.
If however the CFI data rate is lower than the PCM data rate, a minimum CFI date rate
relative to the PCM data rate must be maintained (refer also to examples below).
Another important restriction is, that the number of bits per CFI frame must always be
modulo 16.
Examples
If the PCM frame consists of 32 time slots (2.048 Mbit/s), the minimum possible CFI data
rate in CFI mode 0 is (32 32)/3 = 341.3 kbit/s or if rounded to an integer number of time
slots 344 kbit/s. It is thus not possible to have an IOM-1 interface with 256 kbit/s together
with a 2.048 Mbit/s PCM interface in CFI mode 0. If instead the PCM frame consists of
24 time slots (1.536 Mbit/s), the IOM-1 data rate of 256 kbit/s is feasible since
(24
32)/3 = 256 kbit/s.
CFI Clock and Framing Signal Source CMD1:CSS
The PCM interface is always clocked and synchronized by the PDC and PFS input
signals. The configurable interface however can be clocked and synchronized either by
signals internally derived from PDC and PFS or it can be clocked and synchronized by
the externally applied DCL and FSC input signals.
If PDC and PFS are selected as clock and framing signal source (CMD1:CSS = 0),
the CFI reference clock CRCL is obtained out of PDC after division by 1, 1.5 or 2
according to the prescaler selection (CMD:CSP1 … 0). The CFI frame structure is
synchronized by the PFS input signal. The EPIC generates DCL and FSC as output
signals which may be specified by CMD2:COC (DCL clock rate) and CMD2:FC2 … 0
(FSC pulse form). This mode should be selected whenever the required CFI data rate
can be obtained out of the PCM clock source using the internal prescalers. An overview
of the different possibilities to generate the PCM and CFI data and clock rates for
CMD1:CSS = 0 is given in figure 30.
Semiconductor Group
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