PEF2054NV21XT Infineon Technologies, PEF2054NV21XT Datasheet - Page 48

• Manufacturer Part Number: PEF2054NV21XT
• Manufacturer: Infineon Technologies

Specifications of PEF2054NV21XT

• Lead Free Status / Rohs Status: Compliant

Semiconductor Group
4.2
4.2.1
4.2.1.1 PCM-Mode Register (PMOD)
Access in demultiplexed P-interface mode:
Access in multiplexed P-interface mode:
Reset value: 00
PMD1..0
PCR
Note: Only single clock rate is allowed in PCM-mode 2!
PSM
bit 7
PMD1
Detailed Register Description
PCM Interface Registers
PCM Mode. Defines the actual number of PCM ports, the data rate range and
the data rate stepping.
PMD1..0
00
01
10
The actual selection of physical pins is described below (AIS1/0).
PCM Clock Rate.
0… single clock rate, data rate is identical with the clock frequency supplied
1… double clock rate, data rate is half the clock frequency supplied on pin
PCM Synchronization Mode.
A rising edge on PFS synchronizes the PCM frame. PFS is not evaluated
directly but is sampled with PDC.
0… the external PFS is evaluated with the falling edge of PDC. The internal
1… the external PFS is evaluated with the rising edge of PDC. The internal
PMD0
on pin PDC.
PDC.
PFS (internal frame start) occurs with the next rising edge of PDC.
PFS (internal frame start) occurs with this rising edge of PDC.
H
PCM
Mode
0
1
2
PCR
PSM
Port
Count
4
2
1
48
AIS1
min.
256
512
1024
read/write
read/write
Detailed Register Description
Data Rate
AIS0
[kbit/s]
max.
2048
4096
8192
address: 0
OMDR:RBS = 1
address: 20
AIC1
Data Rate
Stepping
[kbit/s]
256
512
1024
PEB 2055
PEF 2055
H
bit 0
,
H
AIC0