PEF2054NV21XT Infineon Technologies, PEF2054NV21XT Datasheet - Page 35

• Manufacturer Part Number: PEF2054NV21XT
• Manufacturer: Infineon Technologies

Specifications of PEF2054NV21XT

• Lead Free Status / Rohs Status: Compliant

direction is also referred to as the upstream direction, whereas the receive direction is
referred to as the downstream direction.
Data is transmitted and received at normal TTL / CMOS-levels, the output drivers being
of the tristate type. Unassigned time slots may be either be tristated, or programmed to
transmit a defined idle value. The selection of the states “high impedance” and “idle
value” can be performed with a two bit resolution. This tristate capability allows several
devices to be connected together for concentrator functions. If the output driver
capability of the EPIC should prove to be insufficient for a specific application, an
external driver controlled by the TSC can be connected.
The PCM-standby function makes it possible to switch all PCM-output lines to high
impedance with a single command. Internally, the device still works normally. Only the
output drivers are switched off.
The number of time slots per 8-kHz frame is programmable in a wide range (from 4 to
128). In other words, the PCM-data rate can range between 256 kbit/s up to
8.192 Mbit/s. Since the overall switching capacity is limited to 128 time slots per
direction, the number of PCM-ports also depends on the required number of time slots:
in case of 32 time slots per frame (2.048 Mbit/s) for example, four highways are
available, in case of 128 time slots per frame (8.192 Mbit/s), only one highway is
available.
The partitioning between number of ports and number of bits per frame is defined by the
PCM mode. There are three PCM-modes.
The timing characteristics at the PCM interface (data rate, bit shift, etc.) can be varied in
a wide range, but they are the same for each of the four PCM ports, i.e. if a data rate of
2.048 Mbit/s is selected, all four ports run at this data rate of 2.048 Mbit/s.
The PCM-interface has to be clocked with a PCM Data Clock (PDC) signal having a
frequency equal to or twice the selected PCM-data rate. In single clock rate operation,
a frame consisting of 32 time slots, for example, requires a PDC of 2.048 MHz. In double
clock rate operation, however, the same frame structure would require a PDC of
4.096 MHz.
For the synchronization of the time slot structure to an external PCM system, a PCM
Framing Signal (PFS) must be applied. The EPIC evaluates the rising PFS edge to
reset the internal time slot counters. In order to adapt the PFS timing to different timing
requirements, the EPIC can latch the PFS-signal with either the rising or the falling PDC
edge. The PFS signal defines the position of the first bit of the internal PCM frame. The
actual position of the external upstream and downstream PCM frames with respect to
the framing signal PFS can still be adjusted using the PCM offset function of the EPIC.
3.4.1
The serial PCM interface provides up to four duplex ports consisting each of a data
transmit (TxD), a data receive (RxD) and a tristate control (TSC) line. The transmit
Semiconductor Group
PCM-Interface
35
Operational Description
PEB 2055
PEF 2055