MT29F1G08ABADAH4:D Micron Technology Inc, MT29F1G08ABADAH4:D Datasheet - Page 41
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MT29F1G08ABADAH4:D
Manufacturer Part Number
MT29F1G08ABADAH4:D
Description
MICMT29F1G08ABADAH4:D 1GB SLC NAND BGA
Manufacturer
Micron Technology Inc
Datasheet
1.MT29F1G08ABADAH4D.pdf
(93 pages)
Specifications of MT29F1G08ABADAH4:D
Cell Type
NAND
Density
8Gb
Interface Type
Parallel
Address Bus
27b
Operating Supply Voltage (typ)
3.3V
Operating Temp Range
0C to 70C
Package Type
VFBGA
Sync/async
Asynchronous
Operating Temperature Classification
Commercial
Operating Supply Voltage (min)
2.7V
Operating Supply Voltage (max)
3.6V
Word Size
8b
Number Of Words
128M
Supply Current
35mA
Mounting
Surface Mount
Pin Count
63
Lead Free Status / Rohs Status
Supplier Unconfirmed
Available stocks
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Part Number
Manufacturer
Quantity
Price
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MT29F1G08ABADAH4:D
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ROHM
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Part Number:
MT29F1G08ABADAH4:D
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Part Number:
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Micron Technology Inc
Quantity:
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Table 10: Feature Address 90h – Array Operation Mode
SET FEATURES (EFh)
Figure 28: SET FEATURES (EFh) Operation
PDF: 09005aef83e5ffed
m68a.pdf – Rev. D 06/10 EN
P1
Operation
mode option
P2
Reserved
P3
Reserved
P4
Reserved
Subfeature
Parameter
Normal
OTP
operation
OTP
protection
Disable ECC
Enable ECC
Options
Note:
The SET FEATURES (EFh) command writes the subfeature parameters (P1–P4) to the
specified feature address to enable or disable target-specific features. This command is
accepted by the target only when all die (LUNs) on the target are idle.
Writing EFh to the command register puts the target in the set features mode. The tar-
get stays in this mode until another command is issued.
The EFh command is followed by a valid feature address. The host waits for
the subfeature parameters are input. When the asynchronous interface is active, one
subfeature parameter is latched per rising edge of WE#.
After all four subfeature parameters are input, the target goes busy for
STATUS (70h) command can be used to monitor for command completion.
Feature address 01h (timing mode) operation is unique. If SET FEATURES is used to
modify the interface type, the target will be busy for
1. These bits are reset to 00h on power cycle.
1/O7
Cycle type
I/O[7:0]
R/B#
I/O6
Reserved (0)
Reserved (0)
Command
EFh
I/O5
Reserved (0)
Address
FA
Reserved (0)
Reserved (0)
41
I/O4
Reserved (0)
Reserved (0)
Reserved (0)
t ADL
I/O3
D
Micron Technology, Inc. reserves the right to change products or specifications without notice.
P1
0
1
IN
1Gb x8, x16: NAND Flash Memory
D
I/O2
P2
IN
0
0
t
ITC.
D
P3
IN
I/O1
1
0
0
Feature Operations
© 2010 Micron Technology, Inc. All rights reserved.
D
P4
IN
I/O0
t WB
0
1
1
0
0
t
FEAT. The READ
t FEAT
Value
00h
01h
03h
00h
08h
00h
00h
00h
t
ADL before
Notes
1
1
1